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Only store the actual address for completed loads/stores

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This is only needed for RVFI tracing and for xtval if we trap, so we
never need the full capability.
This commit is contained in:
Jessica Clarke
2020-07-14 14:11:10 +01:00
parent e89f7a8130
commit 9bdf71ee4e
3 changed files with 11 additions and 11 deletions
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4
src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv
View File

@@ -207,7 +207,7 @@ function Maybe#(RVFI_DII_Execution#(DataSz,DataSz)) genRVFI(ToReorderBuffer rot,
end
case (rot.ppc_vaddr_csrData) matches
tagged VAddr .vaddr: begin
addr = getAddr(vaddr);
addr = vaddr;
case (rot.lsqTag) matches
tagged Ld .l: rmask = rot.traceBundle.memByteEn;
tagged St .s: begin
@@ -652,7 +652,7 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
vaddr = getAddr(x.pc);
end
else if(x.ppc_vaddr_csrData matches tagged VAddr .va) begin
vaddr = getAddr(va);
vaddr = va;
end
let commitTrap_val = Valid (CommitTrap {
trap: trap,

4
src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv
View File

@@ -178,7 +178,7 @@ interface MemExeInput;
// ROB
method CapMem rob_getPC(InstTag t);
method Action rob_setExecuted_doFinishMem(InstTag t,
CapMem vaddr,
Addr vaddr,
Data store_data, ByteEn store_data_BE,
Bool access_at_commit, Bool non_mmio_st_done
`ifdef RVFI
@@ -603,7 +603,7 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
if (x.capException matches tagged Valid .c) cause = Valid(CapException(c));
Bool access_at_commit = !isValid(cause) && (isMMIO || isLrScAmo);
Bool non_mmio_st_done = !isValid(cause) && !isMMIO && x.mem_func == St;
inIfc.rob_setExecuted_doFinishMem(x.tag, cast(x.vaddr), store_data, store_data_BE,
inIfc.rob_setExecuted_doFinishMem(x.tag, getAddr(x.vaddr), store_data, store_data_BE,
access_at_commit, non_mmio_st_done
`ifdef RVFI
, ExtraTraceBundle{

14
src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv
View File

@@ -62,7 +62,7 @@ import Cur_Cycle :: *;
// vaddr is only used by mem inst in page fault
typedef union tagged {
CapMem PPC; // at default store ppc
CapMem VAddr; // for mem inst, store vaddr
Addr VAddr; // for mem inst, store vaddr
CapMem CSRData; // for Csr inst, store csr_data
} PPCVAddrCSRData deriving(Bits, FShow);
@@ -169,7 +169,7 @@ interface ReorderBufferRowEhr#(numeric type aluExeNum, numeric type fpuMulDivExe
// perform), and non-MMIO St can become Executed (NOTE faulting
// instructions are not Executed, they are set at deqLSQ time)
method Action setExecuted_doFinishMem(CapMem vaddr,
method Action setExecuted_doFinishMem(Addr vaddr,
Data store_data, ByteEn store_data_BE,
Bool access_at_commit, Bool non_mmio_st_done
`ifdef RVFI
@@ -362,9 +362,9 @@ module mkReorderBufferRowEhr(ReorderBufferRowEhr#(aluExeNum, fpuMulDivExeNum)) p
interface setExecuted_doFinishFpuMulDiv = fpuMulDivExe;
method Action setExecuted_doFinishMem(CapMem vaddr,
Data store_data, ByteEn store_data_BE,
Bool access_at_commit, Bool non_mmio_st_done
method Action setExecuted_doFinishMem(Addr vaddr,
Data store_data, ByteEn store_data_BE,
Bool access_at_commit, Bool non_mmio_st_done
`ifdef RVFI
, ExtraTraceBundle tb
`endif
@@ -625,7 +625,7 @@ interface SupReorderBuffer#(numeric type aluExeNum, numeric type fpuMulDivExeNum
interface Vector#(fpuMulDivExeNum, ROB_setExecuted_doFinishFpuMulDiv) setExecuted_doFinishFpuMulDiv;
// doFinishMem, after addr translation
method Action setExecuted_doFinishMem(InstTag x,
CapMem vaddr,
Addr vaddr,
Data store_data, ByteEn store_data_BE,
Bool access_at_commit, Bool non_mmio_st_done
`ifdef RVFI
@@ -1248,7 +1248,7 @@ module mkSupReorderBuffer#(
interface setExecuted_doFinishFpuMulDiv = fpuMulDivSetExeIfc;
method Action setExecuted_doFinishMem(
InstTag x, CapMem vaddr, Data store_data, ByteEn store_data_BE, Bool access_at_commit,
InstTag x, Addr vaddr, Data store_data, ByteEn store_data_BE, Bool access_at_commit,
Bool non_mmio_st_done
`ifdef RVFI
, tb