Cheri-research/Toooba
1
0
Fork 0
Code Issues 1 Pull Requests Actions Packages Projects Releases Wiki Activity

Regenerate verilog

Browse Source
This commit is contained in:
Peter Rugg
2020-06-24 21:16:57 +01:00
parent 86e143a9f7
commit a5578a715a
294 changed files with 77494 additions and 70004 deletions
Download Patch File Download Diff File Expand all files Collapse all files

354
src_SSITH_P3/Verilog_RTL_sim/mkDebug_Module.v
View File

@@ -1,7 +1,7 @@
//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
// On Wed Jun 17 12:20:57 BST 2020
// On Wed Jun 24 20:10:12 BST 2020
//
//
// Ports:
@@ -72,9 +72,11 @@
// ndm_reset_client_response_put I 1 reg
// master_awready I 1
// master_wready I 1
// master_bvalid I 1
// master_bid I 4
// master_bresp I 2
// master_arready I 1
// master_rvalid I 1
// master_rid I 4
// master_rdata I 64
// master_rresp I 2
@@ -88,8 +90,6 @@
// EN_hart0_fpr_mem_client_response_put I 1
// EN_hart0_csr_mem_client_response_put I 1
// EN_ndm_reset_client_response_put I 1
// master_bvalid I 1
// master_rvalid I 1
// EN_dmi_read_data I 1
// EN_hart0_reset_client_request_get I 1
// EN_hart0_client_run_halt_request_get I 1
@@ -101,265 +101,265 @@
//
// Combinational paths from inputs to outputs:
// (dmi_write_dm_addr,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_dmi_write,
// master_rvalid) -> master_awid
// (dmi_write_dm_addr,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_dmi_write,
// master_rvalid) -> master_awaddr
// (dmi_write_dm_addr,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_dmi_write,
// master_rvalid) -> master_awlen
// (dmi_write_dm_addr,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_dmi_write,
// master_rvalid) -> master_awsize
// (dmi_write_dm_addr,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_dmi_write,
// master_rvalid) -> master_awburst
// (dmi_write_dm_addr,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_dmi_write,
// master_rvalid) -> master_awlock
// (dmi_write_dm_addr,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_dmi_write,
// master_rvalid) -> master_awcache
// (dmi_write_dm_addr,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_dmi_write,
// master_rvalid) -> master_awprot
// (dmi_write_dm_addr,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_dmi_write,
// master_rvalid) -> master_awqos
// (dmi_write_dm_addr,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_dmi_write,
// master_rvalid) -> master_awregion
// (dmi_write_dm_addr,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_dmi_write,
// master_rvalid) -> master_awuser
// (dmi_write_dm_addr,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_dmi_write,
// master_rvalid) -> master_awvalid
// (dmi_write_dm_addr,
// dmi_write_dm_word,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_dmi_write,
// master_rvalid) -> master_wdata
// (dmi_write_dm_addr,
// dmi_write_dm_word,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_dmi_write,
// master_rvalid) -> master_wstrb
// (dmi_write_dm_addr,
// dmi_write_dm_word,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_dmi_write,
// master_rvalid) -> master_wlast
// (dmi_write_dm_addr,
// dmi_write_dm_word,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_dmi_write,
// master_rvalid) -> master_wuser
// (dmi_write_dm_addr,
// dmi_write_dm_word,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_dmi_write,
// master_rvalid) -> master_wvalid
// (dmi_write_dm_addr,
// dmi_write_dm_word,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_dmi_write,
// master_rvalid,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_dmi_write) -> master_awid
// (dmi_write_dm_addr,
// master_rvalid,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_dmi_write) -> master_awaddr
// (dmi_write_dm_addr,
// master_rvalid,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_dmi_write) -> master_awlen
// (dmi_write_dm_addr,
// master_rvalid,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_dmi_write) -> master_awsize
// (dmi_write_dm_addr,
// master_rvalid,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_dmi_write) -> master_awburst
// (dmi_write_dm_addr,
// master_rvalid,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_dmi_write) -> master_awlock
// (dmi_write_dm_addr,
// master_rvalid,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_dmi_write) -> master_awcache
// (dmi_write_dm_addr,
// master_rvalid,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_dmi_write) -> master_awprot
// (dmi_write_dm_addr,
// master_rvalid,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_dmi_write) -> master_awqos
// (dmi_write_dm_addr,
// master_rvalid,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_dmi_write) -> master_awregion
// (dmi_write_dm_addr,
// master_rvalid,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_dmi_write) -> master_awuser
// (dmi_write_dm_addr,
// master_rvalid,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_dmi_write) -> master_awvalid
// (dmi_write_dm_addr,
// dmi_write_dm_word,
// master_rvalid,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_dmi_write) -> master_wdata
// (dmi_write_dm_addr,
// dmi_write_dm_word,
// master_rvalid,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_dmi_write) -> master_wstrb
// (dmi_write_dm_addr,
// dmi_write_dm_word,
// master_rvalid,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_dmi_write) -> master_wlast
// (dmi_write_dm_addr,
// dmi_write_dm_word,
// master_rvalid,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_dmi_write) -> master_wuser
// (dmi_write_dm_addr,
// dmi_write_dm_word,
// master_rvalid,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_dmi_write) -> master_wvalid
// (dmi_write_dm_addr,
// dmi_write_dm_word,
// master_rvalid,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_dmi_write,
// EN_dmi_read_data) -> master_arid
// (dmi_write_dm_addr,
// dmi_write_dm_word,
// master_rvalid,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_dmi_write,
// master_rvalid,
// EN_dmi_read_data) -> master_araddr
// (dmi_write_dm_addr,
// dmi_write_dm_word,
// master_rvalid,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_dmi_write,
// master_rvalid,
// EN_dmi_read_data) -> master_arlen
// (dmi_write_dm_addr,
// dmi_write_dm_word,
// master_rvalid,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_dmi_write,
// master_rvalid,
// EN_dmi_read_data) -> master_arsize
// (dmi_write_dm_addr,
// dmi_write_dm_word,
// master_rvalid,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_dmi_write,
// master_rvalid,
// EN_dmi_read_data) -> master_arburst
// (dmi_write_dm_addr,
// dmi_write_dm_word,
// master_rvalid,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_dmi_write,
// master_rvalid,
// EN_dmi_read_data) -> master_arlock
// (dmi_write_dm_addr,
// dmi_write_dm_word,
// master_rvalid,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_dmi_write,
// master_rvalid,
// EN_dmi_read_data) -> master_arcache
// (dmi_write_dm_addr,
// dmi_write_dm_word,
// master_rvalid,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_dmi_write,
// master_rvalid,
// EN_dmi_read_data) -> master_arprot
// (dmi_write_dm_addr,
// dmi_write_dm_word,
// master_rvalid,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_dmi_write,
// master_rvalid,
// EN_dmi_read_data) -> master_arqos
// (dmi_write_dm_addr,
// dmi_write_dm_word,
// master_rvalid,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_dmi_write,
// master_rvalid,
// EN_dmi_read_data) -> master_arregion
// (dmi_write_dm_addr,
// dmi_write_dm_word,
// master_rvalid,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_dmi_write,
// master_rvalid,
// EN_dmi_read_data) -> master_aruser
// (dmi_write_dm_addr,
// dmi_write_dm_word,
// master_rvalid,
// master_rid,
// master_rdata,
// master_rresp,
// master_rlast,
// master_ruser,
// EN_dmi_write,
// master_rvalid,
// EN_dmi_read_data) -> master_arvalid
// EN_dmi_read_data -> dmi_read_data
//
@@ -482,9 +482,9 @@ module mkDebug_Module(CLK,
master_wready,
master_bvalid,
master_bid,
master_bresp,
master_bvalid,
master_bready,
@@ -512,12 +512,12 @@ module mkDebug_Module(CLK,
master_arready,
master_rvalid,
master_rid,
master_rdata,
master_rresp,
master_rlast,
master_ruser,
master_rvalid,
master_rready);
input CLK;
@@ -661,9 +661,9 @@ module mkDebug_Module(CLK,
input master_wready;
// action method master_b_bflit
input master_bvalid;
input [3 : 0] master_bid;
input [1 : 0] master_bresp;
input master_bvalid;
// value method master_b_bready
output master_bready;
@@ -707,12 +707,12 @@ module mkDebug_Module(CLK,
input master_arready;
// action method master_r_rflit
input master_rvalid;
input [3 : 0] master_rid;
input [63 : 0] master_rdata;
input [1 : 0] master_rresp;
input master_rlast;
input master_ruser;
input master_rvalid;
// value method master_r_rready
output master_rready;
@@ -928,8 +928,8 @@ module mkDebug_Module(CLK,
// declarations used by system tasks
// synopsys translate_off
reg [31 : 0] v__h756;
reg [31 : 0] v__h750;
reg [31 : 0] v__h772;
reg [31 : 0] v__h766;
// synopsys translate_on
// action method dmi_read_addr
@@ -1173,7 +1173,7 @@ module mkDebug_Module(CLK,
// action method master_b_bflit
assign CAN_FIRE_master_b_bflit = 1'd1 ;
assign WILL_FIRE_master_b_bflit = master_bvalid ;
assign WILL_FIRE_master_b_bflit = 1'd1 ;
// value method master_b_bready
assign master_bready = dm_system_bus$master_bready ;
@@ -1217,7 +1217,7 @@ module mkDebug_Module(CLK,
// action method master_r_rflit
assign CAN_FIRE_master_r_rflit = 1'd1 ;
assign WILL_FIRE_master_r_rflit = master_rvalid ;
assign WILL_FIRE_master_r_rflit = 1'd1 ;
// value method master_r_rready
assign master_rready = dm_system_bus$master_rready ;
@@ -1299,19 +1299,19 @@ module mkDebug_Module(CLK,
.master_awready(dm_system_bus$master_awready),
.master_bid(dm_system_bus$master_bid),
.master_bresp(dm_system_bus$master_bresp),
.master_bvalid(dm_system_bus$master_bvalid),
.master_rdata(dm_system_bus$master_rdata),
.master_rid(dm_system_bus$master_rid),
.master_rlast(dm_system_bus$master_rlast),
.master_rresp(dm_system_bus$master_rresp),
.master_ruser(dm_system_bus$master_ruser),
.master_rvalid(dm_system_bus$master_rvalid),
.master_wready(dm_system_bus$master_wready),
.write_dm_addr(dm_system_bus$write_dm_addr),
.write_dm_word(dm_system_bus$write_dm_word),
.EN_reset(dm_system_bus$EN_reset),
.EN_av_read(dm_system_bus$EN_av_read),
.EN_write(dm_system_bus$EN_write),
.master_bvalid(dm_system_bus$master_bvalid),
.master_rvalid(dm_system_bus$master_rvalid),
.RDY_reset(dm_system_bus$RDY_reset),
.av_read(dm_system_bus$av_read),
.RDY_av_read(dm_system_bus$RDY_av_read),
@@ -1474,11 +1474,13 @@ module mkDebug_Module(CLK,
assign dm_system_bus$master_awready = master_awready ;
assign dm_system_bus$master_bid = master_bid ;
assign dm_system_bus$master_bresp = master_bresp ;
assign dm_system_bus$master_bvalid = master_bvalid ;
assign dm_system_bus$master_rdata = master_rdata ;
assign dm_system_bus$master_rid = master_rid ;
assign dm_system_bus$master_rlast = master_rlast ;
assign dm_system_bus$master_rresp = master_rresp ;
assign dm_system_bus$master_ruser = master_ruser ;
assign dm_system_bus$master_rvalid = master_rvalid ;
assign dm_system_bus$master_wready = master_wready ;
assign dm_system_bus$write_dm_addr = dmi_write_dm_addr ;
assign dm_system_bus$write_dm_word = dmi_write_dm_word ;
@@ -1501,8 +1503,6 @@ module mkDebug_Module(CLK,
dmi_write_dm_addr == 7'h3D ||
dmi_write_dm_addr == 7'h3E ||
dmi_write_dm_addr == 7'h3F) ;
assign dm_system_bus$master_bvalid = master_bvalid ;
assign dm_system_bus$master_rvalid = master_rvalid ;
// submodule f_read_addr
assign f_read_addr$D_IN = dmi_read_addr_dm_addr ;
@@ -1519,12 +1519,12 @@ module mkDebug_Module(CLK,
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset)
begin
v__h756 = $stime;
v__h772 = $stime;
#0;
end
v__h750 = v__h756 / 32'd10;
v__h766 = v__h772 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset) $display("%0d: Debug_Module reset", v__h750);
if (WILL_FIRE_RL_rl_reset) $display("%0d: Debug_Module reset", v__h766);
end
// synopsys translate_on
endmodule // mkDebug_Module