Fold the fragment count into the standard pipeline structs.
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@@ -186,6 +186,7 @@ typedef struct {
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`ifdef RVFI_DII
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Dii_Parcel_Id dii_pid;
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`endif
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Bit#(TLog#(SupSizeX2)) inst_frags_fetched;
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Maybe#(PcCompressed) pred_next_pc;
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Bool decode_epoch;
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Epoch main_epoch;
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@@ -196,6 +197,7 @@ typedef struct {
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`ifdef RVFI_DII
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Dii_Parcel_Id dii_pid;
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`endif
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Bit#(TLog#(SupSizeX2)) inst_frags_fetched;
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Maybe#(PcCompressed) pred_next_pc;
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Maybe#(Exception) cause;
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Bool access_mmio; // inst fetch from MMIO
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@@ -362,8 +364,8 @@ module mkFetchStage(FetchStage);
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Reg#(Epoch) f_main_epoch <- mkReg(0); // fetch estimate of main epoch
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// Pipeline Stage FIFOs
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Fifo#(2, Tuple2#(Bit#(TLog#(SupSizeX2)),Fetch1ToFetch2)) f12f2 <- mkCFFifo;
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Fifo#(4, Tuple2#(Bit#(TLog#(SupSizeX2)),Fetch2ToFetch3)) f22f3 <- mkCFFifo; // FIFO should match I$ latency
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Fifo#(2, Fetch1ToFetch2) f12f2 <- mkCFFifo;
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Fifo#(4, Fetch2ToFetch3) f22f3 <- mkCFFifo; // FIFO should match I$ latency
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// These two fifos needs a capacity of 3 for full throughput if we fire only when we can enq on on channels.
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SupFifo#(SupSizeX2, 3, Fetch3ToDecode) f32d <- mkUGSupFifo; // Unguarded to prevent the static analyser from exploding.
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SupFifo#(SupSize, 3, FromFetchStage) out_fifo <- mkSupFifo;
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@@ -470,17 +472,18 @@ module mkFetchStage(FetchStage);
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`ifdef RVFI_DII
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dii_pid: dii_pid,
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`endif
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inst_frags_fetched: posLastSupX2,
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pred_next_pc: isValid(pred_next_pc) ?
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Valid(compressPc(ppc_idx, validValue(pred_next_pc))) : Invalid,
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decode_epoch: decode_epoch[0],
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main_epoch: f_main_epoch};
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f12f2.enq(tuple2(posLastSupX2,out));
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f12f2.enq(out);
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if (verbose) $display("Fetch1: ", fshow(out), " posLastSupX2: %d", posLastSupX2);
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endrule
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rule doFetch2;
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let {nbSupX2,in} = f12f2.first;
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let in = f12f2.first;
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f12f2.deq;
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// Get TLB response
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@@ -511,7 +514,7 @@ module mkFetchStage(FetchStage);
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// cache line size, so all nbSup+1 insts can be fetched
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// from boot rom. It won't happen that insts fetched from
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// boot rom is less than requested.
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mmio.bootRomReq(phys_pc, nbSupX2);
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mmio.bootRomReq(phys_pc, in.inst_frags_fetched);
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access_mmio = True;
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`ifdef DEBUG_WEDGE
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lastImemReq <= phys_pc;
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@@ -539,17 +542,18 @@ module mkFetchStage(FetchStage);
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`ifdef RVFI_DII
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dii_pid: in.dii_pid,
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`endif
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inst_frags_fetched: in.inst_frags_fetched,
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pred_next_pc: in.pred_next_pc,
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cause: cause,
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access_mmio: access_mmio,
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decode_epoch: in.decode_epoch,
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main_epoch: in.main_epoch };
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f22f3.enq(tuple2(nbSupX2,out));
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f22f3.enq(out);
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if (verbosity >= 2) begin
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$display ("----------------");
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$display ("Fetch2: TLB response pyhs_pc 0x%0h cause ", phys_pc, fshow (cause));
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$display ("Fetch2: f2_tof3.enq: nbSupX2 %0d out ", nbSupX2, fshow (out));
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$display ("----------------");
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$display ("Fetch2: TLB response pyhs_pc 0x%0h cause ", phys_pc, fshow (cause));
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$display ("Fetch2: f2_tof3.enq: out ", fshow (out));
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end
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endrule
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@@ -557,10 +561,10 @@ module mkFetchStage(FetchStage);
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Vector#(SupSizeX2,Integer) indexes = genVector;
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function Bool f32d_lane_notFull(Integer i) = f32d.enqS[i].canEnq;
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rule doFetch3(all(f32d_lane_notFull, indexes));
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let {nbSupX2In, fetch3In} = f22f3.first;
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let fetch3In = f22f3.first;
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if (verbosity >= 2) begin
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if (f22f3.notEmpty)
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$display("Fetch3: nbSupX2In: %0d fetch3In: ", nbSupX2In, fshow (fetch3In));
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$display("Fetch3: fetch3In: ", fshow (fetch3In));
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else
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$display("Fetch3: Nothing else from Fetch2");
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end
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@@ -592,7 +596,7 @@ module mkFetchStage(FetchStage);
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`endif
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end
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for (Integer i = 0; i < valueOf(SupSizeX2) && fromInteger(i) <= nbSupX2In; i = i + 1) begin
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for (Integer i = 0; i < valueOf(SupSizeX2) && fromInteger(i) <= fetch3In.inst_frags_fetched; i = i + 1) begin
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PcCompressed pc = fetch3In.pc;
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pc.lsb = pc.lsb + (2 * fromInteger(i));
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f32d.enqS[i].enq (Fetch3ToDecode {
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@@ -600,7 +604,7 @@ module mkFetchStage(FetchStage);
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`ifdef RVFI_DII
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dii_pid: fetch3In.dii_pid + fromInteger(i),
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`endif
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ppc: (fromInteger(i)==nbSupX2In) ? fetch3In.pred_next_pc : Invalid,
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ppc: (fromInteger(i)==fetch3In.inst_frags_fetched) ? fetch3In.pred_next_pc : Invalid,
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inst_frag: validValue(inst_d[i]),
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cause: fetch3In.cause,
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decode_epoch: fetch3In.decode_epoch,
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