added working paging small kernel
This commit is contained in:
40
Tests/isa/Cprograms/build.sh
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40
Tests/isa/Cprograms/build.sh
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@@ -0,0 +1,40 @@
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# scp encoding.h home-1:/home/akilan/
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# scp entry.S home-1:/home/akilan/
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# scp link.ld home-1:/home/akilan/
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# scp riscv_test_p.h home-1:/home/akilan/
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# scp riscv_test.h home-1:/home/akilan/
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# scp string.c home-1:/home/akilan/
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# scp vm.c home-1:/home/akilan/
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# scp test.S home-1:/home/akilan/
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# scp test_macros.h home-1:/home/akilan/
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# GCC compile
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# ssh home-1 'cd /home/akilan/ && export PATH=/opt/riscv/bin:$PATH && riscv64-unknown-elf-gcc -DENTROPY=0xf21e02b -mcmodel=medany -nostdlib -nostartfiles -ffreestanding -fno-builtin -mabi=lp64 -T link.ld vm.c string.c entry.S test.S -o testC'
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# Clang compile (architecture Regular RISCV)
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ssh home-1 'clang --target=riscv64-unknown-elf -DENTROPY=0xf21e02b --gcc-toolchain=/opt/riscv -mcmodel=medany -nostdlib -nostartfiles -ffreestanding -fno-builtin -mabi=lp64 -T link.ld vm.c string.c entry.S test.S -o testC'
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# Clang using the cheri clang compiler
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scp home-1:/home/akilan/testC .
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export PATH=/home/akilan/cheri/output/sdk/bin/clang:$PATH
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# riscv64-unknown-elf-gcc \
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# -march=rv64imac \
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# -mabi=lp64 \
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# -nostartfiles \
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# -fno-builtin \
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# -T link.ld \
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# entry.S vm.c string.c \
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# clang \
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# --target=riscv64-unknown-elf \
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# -march=rv64imac \
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# -mabi=lp64 \
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# -nostdlib \
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# -nostartfiles \
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# -fuse-ld=lld \
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# -T link.ld \
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# entry.S vm.c string.c \
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# -I. \
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# -o output.elf
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5013
Tests/isa/Cprograms/encoding.h
Normal file
5013
Tests/isa/Cprograms/encoding.h
Normal file
File diff suppressed because it is too large
Load Diff
164
Tests/isa/Cprograms/entry.S
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164
Tests/isa/Cprograms/entry.S
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@@ -0,0 +1,164 @@
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#include "riscv_test.h"
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#if __riscv_xlen == 64
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# define STORE sd
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# define LOAD ld
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# define REGBYTES 8
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#else
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# define STORE sw
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# define LOAD lw
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# define REGBYTES 4
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#endif
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#define STACK_TOP (_end + RISCV_PGSIZE * 4)
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.section ".text.init","ax",@progbits
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.globl _start
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.align 2
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_start:
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j handle_reset
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/* NMI vector */
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.align 2
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nmi_vector:
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j wtf
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.align 2
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trap_vector:
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j wtf
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handle_reset:
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li x1, 0
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li x2, 0
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li x3, 0
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li x4, 0
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li x5, 0
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li x6, 0
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li x7, 0
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li x8, 0
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li x9, 0
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li x10, 0
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li x11, 0
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li x12, 0
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li x13, 0
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li x14, 0
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li x15, 0
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li x16, 0
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li x17, 0
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li x18, 0
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li x19, 0
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li x20, 0
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li x21, 0
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li x22, 0
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li x23, 0
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li x24, 0
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li x25, 0
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li x26, 0
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li x27, 0
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li x28, 0
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li x29, 0
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li x30, 0
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li x31, 0
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INIT_RNMI
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la t0, trap_vector
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csrw mtvec, t0
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la sp, STACK_TOP - SIZEOF_TRAPFRAME_T
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csrr t0, mhartid
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slli t0, t0, 12
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add sp, sp, t0
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csrw mscratch, sp
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call extra_boot
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la a0, userstart
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j vm_boot
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.globl pop_tf
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pop_tf:
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LOAD t0,33*REGBYTES(a0)
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csrw sepc,t0
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LOAD x1,1*REGBYTES(a0)
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LOAD x2,2*REGBYTES(a0)
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LOAD x3,3*REGBYTES(a0)
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LOAD x4,4*REGBYTES(a0)
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LOAD x5,5*REGBYTES(a0)
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LOAD x6,6*REGBYTES(a0)
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LOAD x7,7*REGBYTES(a0)
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LOAD x8,8*REGBYTES(a0)
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LOAD x9,9*REGBYTES(a0)
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LOAD x11,11*REGBYTES(a0)
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LOAD x12,12*REGBYTES(a0)
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LOAD x13,13*REGBYTES(a0)
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LOAD x14,14*REGBYTES(a0)
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LOAD x15,15*REGBYTES(a0)
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LOAD x16,16*REGBYTES(a0)
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LOAD x17,17*REGBYTES(a0)
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LOAD x18,18*REGBYTES(a0)
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LOAD x19,19*REGBYTES(a0)
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LOAD x20,20*REGBYTES(a0)
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LOAD x21,21*REGBYTES(a0)
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LOAD x22,22*REGBYTES(a0)
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LOAD x23,23*REGBYTES(a0)
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LOAD x24,24*REGBYTES(a0)
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LOAD x25,25*REGBYTES(a0)
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LOAD x26,26*REGBYTES(a0)
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LOAD x27,27*REGBYTES(a0)
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LOAD x28,28*REGBYTES(a0)
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LOAD x29,29*REGBYTES(a0)
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LOAD x30,30*REGBYTES(a0)
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LOAD x31,31*REGBYTES(a0)
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LOAD a0,10*REGBYTES(a0)
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sret
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.global trap_entry
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.align 2
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trap_entry:
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csrrw sp, sscratch, sp
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# save gprs
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STORE x1,1*REGBYTES(sp)
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STORE x3,3*REGBYTES(sp)
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STORE x4,4*REGBYTES(sp)
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STORE x5,5*REGBYTES(sp)
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STORE x6,6*REGBYTES(sp)
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STORE x7,7*REGBYTES(sp)
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STORE x8,8*REGBYTES(sp)
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STORE x9,9*REGBYTES(sp)
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STORE x10,10*REGBYTES(sp)
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STORE x11,11*REGBYTES(sp)
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STORE x12,12*REGBYTES(sp)
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STORE x13,13*REGBYTES(sp)
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STORE x14,14*REGBYTES(sp)
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STORE x15,15*REGBYTES(sp)
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STORE x16,16*REGBYTES(sp)
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STORE x17,17*REGBYTES(sp)
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STORE x18,18*REGBYTES(sp)
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STORE x19,19*REGBYTES(sp)
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STORE x20,20*REGBYTES(sp)
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STORE x21,21*REGBYTES(sp)
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STORE x22,22*REGBYTES(sp)
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STORE x23,23*REGBYTES(sp)
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STORE x24,24*REGBYTES(sp)
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STORE x25,25*REGBYTES(sp)
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STORE x26,26*REGBYTES(sp)
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STORE x27,27*REGBYTES(sp)
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STORE x28,28*REGBYTES(sp)
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STORE x29,29*REGBYTES(sp)
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STORE x30,30*REGBYTES(sp)
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STORE x31,31*REGBYTES(sp)
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csrrw t0,sscratch,sp
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STORE t0,2*REGBYTES(sp)
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# get sr, epc, badvaddr, cause
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csrr t0,sstatus
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STORE t0,32*REGBYTES(sp)
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csrr t0,sepc
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STORE t0,33*REGBYTES(sp)
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csrr t0,stval
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STORE t0,34*REGBYTES(sp)
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csrr t0,scause
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STORE t0,35*REGBYTES(sp)
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move a0, sp
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j handle_trap
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16
Tests/isa/Cprograms/link.ld
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16
Tests/isa/Cprograms/link.ld
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@@ -0,0 +1,16 @@
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OUTPUT_ARCH( "riscv" )
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ENTRY(_start)
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SECTIONS
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{
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. = 0x80000000;
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.text.init : { *(.text.init) }
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. = ALIGN(0x1000);
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.tohost : { *(.tohost) }
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. = ALIGN(0x1000);
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.text : { *(.text) }
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. = ALIGN(0x1000);
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.data : { *(.data) }
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.bss : { *(.bss) }
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_end = .;
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}
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98
Tests/isa/Cprograms/riscv_test.h
Normal file
98
Tests/isa/Cprograms/riscv_test.h
Normal file
@@ -0,0 +1,98 @@
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// See LICENSE for license details.
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#ifndef _ENV_VIRTUAL_SINGLE_CORE_H
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#define _ENV_VIRTUAL_SINGLE_CORE_H
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#include "riscv_test_p.h"
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//-----------------------------------------------------------------------
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// Begin Macro
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//-----------------------------------------------------------------------
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#undef RVTEST_FP_ENABLE
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#define RVTEST_FP_ENABLE fssr x0
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#undef RVTEST_VECTOR_ENABLE
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#define RVTEST_VECTOR_ENABLE \
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csrwi fcsr, 0; \
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csrwi vcsr, 0;
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#undef RVTEST_ZVE32X_ENABLE
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#define RVTEST_ZVE32X_ENABLE \
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csrwi vcsr, 0;
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#undef RVTEST_CODE_BEGIN
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#define RVTEST_CODE_BEGIN \
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.text; \
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.global extra_boot; \
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extra_boot: \
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EXTRA_INIT \
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ret; \
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.global trap_filter; \
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trap_filter: \
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FILTER_TRAP \
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li a0, 0; \
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ret; \
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.global pf_filter; \
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pf_filter: \
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FILTER_PAGE_FAULT \
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li a0, 0; \
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ret; \
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.global userstart; \
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userstart: \
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init
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//-----------------------------------------------------------------------
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// Pass/Fail Macro
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//-----------------------------------------------------------------------
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#undef RVTEST_PASS
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#define RVTEST_PASS li a0, 1; scall
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#undef RVTEST_FAIL
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#define RVTEST_FAIL sll a0, TESTNUM, 1; 1:beqz a0, 1b; or a0, a0, 1; scall;
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//-----------------------------------------------------------------------
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// Data Section Macro
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//-----------------------------------------------------------------------
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#undef RVTEST_DATA_END
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#define RVTEST_DATA_END
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//-----------------------------------------------------------------------
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// Supervisor mode definitions and macros
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//-----------------------------------------------------------------------
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#ifndef LFSR_BITS
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#define LFSR_BITS 6
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#endif
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#define MAX_TEST_PAGES ((1 << LFSR_BITS)-1) // this must be the period of the LFSR below
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#define LFSR_NEXT(x) (((((x)^((x)>>1)) & 1) << (LFSR_BITS-1)) | ((x) >> 1))
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#define PGSHIFT 12
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#define PGSIZE (1UL << PGSHIFT)
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#define SIZEOF_TRAPFRAME_T ((__riscv_xlen / 8) * 36)
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#ifndef __ASSEMBLER__
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typedef unsigned long pte_t;
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#define LEVELS (sizeof(pte_t) == sizeof(uint64_t) ? 3 : 2)
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#define PTIDXBITS (PGSHIFT - (sizeof(pte_t) == 8 ? 3 : 2))
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#define VPN_BITS (PTIDXBITS * LEVELS)
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#define VA_BITS (VPN_BITS + PGSHIFT)
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#define PTES_PER_PT (1UL << RISCV_PGLEVEL_BITS)
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#define MEGAPAGE_SIZE (PTES_PER_PT * PGSIZE)
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typedef struct
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{
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long gpr[32];
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long sr;
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long epc;
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long badvaddr;
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long cause;
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} trapframe_t;
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#endif
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#endif
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295
Tests/isa/Cprograms/riscv_test_p.h
Normal file
295
Tests/isa/Cprograms/riscv_test_p.h
Normal file
@@ -0,0 +1,295 @@
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// See LICENSE for license details.
|
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#ifndef _ENV_PHYSICAL_SINGLE_CORE_H
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#define _ENV_PHYSICAL_SINGLE_CORE_H
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#include "encoding.h"
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//-----------------------------------------------------------------------
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// Begin Macro
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//-----------------------------------------------------------------------
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#define RVTEST_RV64U \
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.macro init; \
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.endm
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#define RVTEST_RV64UF \
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.macro init; \
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RVTEST_FP_ENABLE; \
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.endm
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#define RVTEST_RV64UV \
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.macro init; \
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RVTEST_VECTOR_ENABLE; \
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.endm
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#define RVTEST_RV64UVX \
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.macro init; \
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RVTEST_ZVE32X_ENABLE; \
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.endm
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#define RVTEST_RV32U \
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.macro init; \
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.endm
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#define RVTEST_RV32UF \
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.macro init; \
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RVTEST_FP_ENABLE; \
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.endm
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#define RVTEST_RV32UV \
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.macro init; \
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RVTEST_VECTOR_ENABLE; \
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.endm
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#define RVTEST_RV32UVX \
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.macro init; \
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RVTEST_ZVE32X_ENABLE; \
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.endm
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#define RVTEST_RV64M \
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.macro init; \
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RVTEST_ENABLE_MACHINE; \
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.endm
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#define RVTEST_RV64S \
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.macro init; \
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RVTEST_ENABLE_SUPERVISOR; \
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.endm
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#define RVTEST_RV32M \
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.macro init; \
|
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RVTEST_ENABLE_MACHINE; \
|
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.endm
|
||||
|
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#define RVTEST_RV32S \
|
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.macro init; \
|
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RVTEST_ENABLE_SUPERVISOR; \
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.endm
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#if __riscv_xlen == 64
|
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# define CHECK_XLEN li a0, 1; slli a0, a0, 31; bgez a0, 1f; RVTEST_PASS; 1:
|
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#else
|
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# define CHECK_XLEN li a0, 1; slli a0, a0, 31; bltz a0, 1f; RVTEST_PASS; 1:
|
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#endif
|
||||
|
||||
#define INIT_XREG \
|
||||
li x1, 0; \
|
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li x2, 0; \
|
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li x3, 0; \
|
||||
li x4, 0; \
|
||||
li x5, 0; \
|
||||
li x6, 0; \
|
||||
li x7, 0; \
|
||||
li x8, 0; \
|
||||
li x9, 0; \
|
||||
li x10, 0; \
|
||||
li x11, 0; \
|
||||
li x12, 0; \
|
||||
li x13, 0; \
|
||||
li x14, 0; \
|
||||
li x15, 0; \
|
||||
li x16, 0; \
|
||||
li x17, 0; \
|
||||
li x18, 0; \
|
||||
li x19, 0; \
|
||||
li x20, 0; \
|
||||
li x21, 0; \
|
||||
li x22, 0; \
|
||||
li x23, 0; \
|
||||
li x24, 0; \
|
||||
li x25, 0; \
|
||||
li x26, 0; \
|
||||
li x27, 0; \
|
||||
li x28, 0; \
|
||||
li x29, 0; \
|
||||
li x30, 0; \
|
||||
li x31, 0;
|
||||
|
||||
#define INIT_PMP \
|
||||
la t0, 1f; \
|
||||
csrw mtvec, t0; \
|
||||
/* Set up a PMP to permit all accesses */ \
|
||||
li t0, (1 << (31 + (__riscv_xlen / 64) * (53 - 31))) - 1; \
|
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csrw pmpaddr0, t0; \
|
||||
li t0, PMP_NAPOT | PMP_R | PMP_W | PMP_X; \
|
||||
csrw pmpcfg0, t0; \
|
||||
.align 2; \
|
||||
1:
|
||||
|
||||
#define INIT_RNMI \
|
||||
la t0, 1f; \
|
||||
csrw mtvec, t0; \
|
||||
csrwi CSR_MNSTATUS, MNSTATUS_NMIE; \
|
||||
.align 2; \
|
||||
1:
|
||||
|
||||
#define INIT_SATP \
|
||||
la t0, 1f; \
|
||||
csrw mtvec, t0; \
|
||||
csrwi satp, 0; \
|
||||
.align 2; \
|
||||
1:
|
||||
|
||||
#define DELEGATE_NO_TRAPS \
|
||||
csrwi mie, 0; \
|
||||
la t0, 1f; \
|
||||
csrw mtvec, t0; \
|
||||
csrwi medeleg, 0; \
|
||||
csrwi mideleg, 0; \
|
||||
.align 2; \
|
||||
1:
|
||||
|
||||
#define RVTEST_ENABLE_SUPERVISOR \
|
||||
li a0, MSTATUS_MPP & (MSTATUS_MPP >> 1); \
|
||||
csrs mstatus, a0; \
|
||||
li a0, SIP_SSIP | SIP_STIP; \
|
||||
csrs mideleg, a0; \
|
||||
|
||||
#define RVTEST_ENABLE_MACHINE \
|
||||
li a0, MSTATUS_MPP; \
|
||||
csrs mstatus, a0; \
|
||||
|
||||
#define RVTEST_FP_ENABLE \
|
||||
li a0, MSTATUS_FS & (MSTATUS_FS >> 1); \
|
||||
csrs mstatus, a0; \
|
||||
csrwi fcsr, 0
|
||||
|
||||
#define RVTEST_VECTOR_ENABLE \
|
||||
li a0, (MSTATUS_VS & (MSTATUS_VS >> 1)) | \
|
||||
(MSTATUS_FS & (MSTATUS_FS >> 1)); \
|
||||
csrs mstatus, a0; \
|
||||
csrwi fcsr, 0; \
|
||||
csrwi vcsr, 0;
|
||||
|
||||
#define RVTEST_ZVE32X_ENABLE \
|
||||
li a0, (MSTATUS_VS & (MSTATUS_VS >> 1)); \
|
||||
csrs mstatus, a0; \
|
||||
csrwi vcsr, 0;
|
||||
|
||||
#define RISCV_MULTICORE_DISABLE \
|
||||
csrr a0, mhartid; \
|
||||
1: bnez a0, 1b
|
||||
|
||||
#define EXTRA_TVEC_USER
|
||||
#define EXTRA_TVEC_MACHINE
|
||||
#define EXTRA_INIT
|
||||
#define EXTRA_INIT_TIMER
|
||||
#define FILTER_TRAP
|
||||
#define FILTER_PAGE_FAULT
|
||||
|
||||
#define INTERRUPT_HANDLER j other_exception /* No interrupts should occur */
|
||||
|
||||
#define RVTEST_CODE_BEGIN \
|
||||
.section .text.init; \
|
||||
.align 6; \
|
||||
.weak stvec_handler; \
|
||||
.weak mtvec_handler; \
|
||||
.globl _start; \
|
||||
_start: \
|
||||
/* reset vector */ \
|
||||
j reset_vector; \
|
||||
.align 2; \
|
||||
trap_vector: \
|
||||
/* test whether the test came from pass/fail */ \
|
||||
csrr t5, mcause; \
|
||||
li t6, CAUSE_USER_ECALL; \
|
||||
beq t5, t6, write_tohost; \
|
||||
li t6, CAUSE_SUPERVISOR_ECALL; \
|
||||
beq t5, t6, write_tohost; \
|
||||
li t6, CAUSE_MACHINE_ECALL; \
|
||||
beq t5, t6, write_tohost; \
|
||||
/* if an mtvec_handler is defined, jump to it */ \
|
||||
la t5, mtvec_handler; \
|
||||
beqz t5, 1f; \
|
||||
jr t5; \
|
||||
/* was it an interrupt or an exception? */ \
|
||||
1: csrr t5, mcause; \
|
||||
bgez t5, handle_exception; \
|
||||
INTERRUPT_HANDLER; \
|
||||
handle_exception: \
|
||||
/* we don't know how to handle whatever the exception was */ \
|
||||
other_exception: \
|
||||
/* some unhandlable exception occurred */ \
|
||||
1: ori TESTNUM, TESTNUM, 1337; \
|
||||
write_tohost: \
|
||||
sw TESTNUM, tohost, t5; \
|
||||
sw zero, tohost + 4, t5; \
|
||||
j write_tohost; \
|
||||
reset_vector: \
|
||||
INIT_XREG; \
|
||||
RISCV_MULTICORE_DISABLE; \
|
||||
INIT_RNMI; \
|
||||
INIT_SATP; \
|
||||
INIT_PMP; \
|
||||
DELEGATE_NO_TRAPS; \
|
||||
li TESTNUM, 0; \
|
||||
la t0, trap_vector; \
|
||||
csrw mtvec, t0; \
|
||||
CHECK_XLEN; \
|
||||
/* if an stvec_handler is defined, delegate exceptions to it */ \
|
||||
la t0, stvec_handler; \
|
||||
beqz t0, 1f; \
|
||||
csrw stvec, t0; \
|
||||
li t0, (1 << CAUSE_LOAD_PAGE_FAULT) | \
|
||||
(1 << CAUSE_STORE_PAGE_FAULT) | \
|
||||
(1 << CAUSE_FETCH_PAGE_FAULT) | \
|
||||
(1 << CAUSE_MISALIGNED_FETCH) | \
|
||||
(1 << CAUSE_USER_ECALL) | \
|
||||
(1 << CAUSE_BREAKPOINT); \
|
||||
csrw medeleg, t0; \
|
||||
1: csrwi mstatus, 0; \
|
||||
init; \
|
||||
EXTRA_INIT; \
|
||||
EXTRA_INIT_TIMER; \
|
||||
la t0, 1f; \
|
||||
csrw mepc, t0; \
|
||||
csrr a0, mhartid; \
|
||||
mret; \
|
||||
1:
|
||||
|
||||
//-----------------------------------------------------------------------
|
||||
// End Macro
|
||||
//-----------------------------------------------------------------------
|
||||
|
||||
#define RVTEST_CODE_END \
|
||||
unimp
|
||||
|
||||
//-----------------------------------------------------------------------
|
||||
// Pass/Fail Macro
|
||||
//-----------------------------------------------------------------------
|
||||
|
||||
#define RVTEST_PASS \
|
||||
fence; \
|
||||
li TESTNUM, 1; \
|
||||
li a7, 93; \
|
||||
li a0, 0; \
|
||||
ecall
|
||||
|
||||
#define TESTNUM gp
|
||||
#define RVTEST_FAIL \
|
||||
fence; \
|
||||
1: beqz TESTNUM, 1b; \
|
||||
sll TESTNUM, TESTNUM, 1; \
|
||||
or TESTNUM, TESTNUM, 1; \
|
||||
li a7, 93; \
|
||||
addi a0, TESTNUM, 0; \
|
||||
ecall
|
||||
|
||||
//-----------------------------------------------------------------------
|
||||
// Data Section Macro
|
||||
//-----------------------------------------------------------------------
|
||||
|
||||
#define EXTRA_DATA
|
||||
|
||||
#define RVTEST_DATA_BEGIN \
|
||||
EXTRA_DATA \
|
||||
.pushsection .tohost,"aw",@progbits; \
|
||||
.align 6; .global tohost; tohost: .dword 0; .size tohost, 8; \
|
||||
.align 6; .global fromhost; fromhost: .dword 0; .size fromhost, 8;\
|
||||
.popsection; \
|
||||
.align 4; .global begin_signature; begin_signature:
|
||||
|
||||
#define RVTEST_DATA_END .align 4; .global end_signature; end_signature:
|
||||
|
||||
#endif
|
||||
114
Tests/isa/Cprograms/string.c
Normal file
114
Tests/isa/Cprograms/string.c
Normal file
@@ -0,0 +1,114 @@
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <ctype.h>
|
||||
|
||||
void* memcpy(void* dest, const void* src, size_t len)
|
||||
{
|
||||
if ((((uintptr_t)dest | (uintptr_t)src | len) & (sizeof(uintptr_t)-1)) == 0) {
|
||||
const uintptr_t* s = src;
|
||||
uintptr_t *d = dest;
|
||||
while (d < (uintptr_t*)(dest + len))
|
||||
*d++ = *s++;
|
||||
} else {
|
||||
const char* s = src;
|
||||
char *d = dest;
|
||||
while (d < (char*)(dest + len))
|
||||
*d++ = *s++;
|
||||
}
|
||||
return dest;
|
||||
}
|
||||
|
||||
void* memset(void* dest, int byte, size_t len)
|
||||
{
|
||||
if ((((uintptr_t)dest | len) & (sizeof(uintptr_t)-1)) == 0) {
|
||||
uintptr_t word = byte & 0xFF;
|
||||
word |= word << 8;
|
||||
word |= word << 16;
|
||||
word |= word << 16 << 16;
|
||||
|
||||
uintptr_t *d = dest;
|
||||
while (d < (uintptr_t*)(dest + len))
|
||||
*d++ = word;
|
||||
} else {
|
||||
char *d = dest;
|
||||
while (d < (char*)(dest + len))
|
||||
*d++ = byte;
|
||||
}
|
||||
return dest;
|
||||
}
|
||||
|
||||
size_t strlen(const char *s)
|
||||
{
|
||||
const char *p = s;
|
||||
while (*p)
|
||||
p++;
|
||||
return p - s;
|
||||
}
|
||||
|
||||
int strcmp(const char* s1, const char* s2)
|
||||
{
|
||||
unsigned char c1, c2;
|
||||
|
||||
do {
|
||||
c1 = *s1++;
|
||||
c2 = *s2++;
|
||||
} while (c1 != 0 && c1 == c2);
|
||||
|
||||
return c1 - c2;
|
||||
}
|
||||
|
||||
int memcmp(const void* s1, const void* s2, size_t n)
|
||||
{
|
||||
if ((((uintptr_t)s1 | (uintptr_t)s2) & (sizeof(uintptr_t)-1)) == 0) {
|
||||
const uintptr_t* u1 = s1;
|
||||
const uintptr_t* u2 = s2;
|
||||
const uintptr_t* end = u1 + (n / sizeof(uintptr_t));
|
||||
while (u1 < end) {
|
||||
if (*u1 != *u2)
|
||||
break;
|
||||
u1++;
|
||||
u2++;
|
||||
}
|
||||
n -= (const void*)u1 - s1;
|
||||
s1 = u1;
|
||||
s2 = u2;
|
||||
}
|
||||
|
||||
while (n--) {
|
||||
unsigned char c1 = *(const unsigned char*)s1++;
|
||||
unsigned char c2 = *(const unsigned char*)s2++;
|
||||
if (c1 != c2)
|
||||
return c1 - c2;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
char* strcpy(char* dest, const char* src)
|
||||
{
|
||||
char* d = dest;
|
||||
while ((*d++ = *src++))
|
||||
;
|
||||
return dest;
|
||||
}
|
||||
|
||||
long atol(const char* str)
|
||||
{
|
||||
long res = 0;
|
||||
int sign = 0;
|
||||
|
||||
while (*str == ' ')
|
||||
str++;
|
||||
|
||||
if (*str == '-' || *str == '+') {
|
||||
sign = *str == '-';
|
||||
str++;
|
||||
}
|
||||
|
||||
while (*str) {
|
||||
res *= 10;
|
||||
res += *str++ - '0';
|
||||
}
|
||||
|
||||
return sign ? -res : res;
|
||||
}
|
||||
25
Tests/isa/Cprograms/test.S
Normal file
25
Tests/isa/Cprograms/test.S
Normal file
@@ -0,0 +1,25 @@
|
||||
#include "riscv_test.h"
|
||||
#include "test_macros.h"
|
||||
|
||||
RVTEST_RV64U # Define TVM used by program.
|
||||
|
||||
# Test code region.
|
||||
RVTEST_CODE_BEGIN # Start of test code.
|
||||
RVTEST_PASS # Signal success.
|
||||
fail:
|
||||
RVTEST_FAIL
|
||||
RVTEST_CODE_END # End of test code.
|
||||
|
||||
# Input data section.
|
||||
# This section is optional, and this data is NOT saved in the output.
|
||||
.data
|
||||
.align 3
|
||||
testdata:
|
||||
.dword 41
|
||||
|
||||
# Output data section.
|
||||
RVTEST_DATA_BEGIN # Start of test output data region.
|
||||
.align 3
|
||||
result:
|
||||
.dword -1
|
||||
RVTEST_DATA_END # End of test output data region.
|
||||
BIN
Tests/isa/Cprograms/testC
Executable file
BIN
Tests/isa/Cprograms/testC
Executable file
Binary file not shown.
832
Tests/isa/Cprograms/test_macros.h
Normal file
832
Tests/isa/Cprograms/test_macros.h
Normal file
@@ -0,0 +1,832 @@
|
||||
// See LICENSE for license details.
|
||||
|
||||
#ifndef __TEST_MACROS_SCALAR_H
|
||||
#define __TEST_MACROS_SCALAR_H
|
||||
|
||||
|
||||
#-----------------------------------------------------------------------
|
||||
# Helper macros
|
||||
#-----------------------------------------------------------------------
|
||||
|
||||
#define MASK_XLEN(x) ((x) & ((1 << (__riscv_xlen - 1) << 1) - 1))
|
||||
|
||||
#define TEST_CASE( testnum, testreg, correctval, code... ) \
|
||||
test_ ## testnum: \
|
||||
li TESTNUM, testnum; \
|
||||
code; \
|
||||
li x7, MASK_XLEN(correctval); \
|
||||
bne testreg, x7, fail;
|
||||
|
||||
# We use a macro hack to simpify code generation for various numbers
|
||||
# of bubble cycles.
|
||||
|
||||
#define TEST_INSERT_NOPS_0
|
||||
#define TEST_INSERT_NOPS_1 nop; TEST_INSERT_NOPS_0
|
||||
#define TEST_INSERT_NOPS_2 nop; TEST_INSERT_NOPS_1
|
||||
#define TEST_INSERT_NOPS_3 nop; TEST_INSERT_NOPS_2
|
||||
#define TEST_INSERT_NOPS_4 nop; TEST_INSERT_NOPS_3
|
||||
#define TEST_INSERT_NOPS_5 nop; TEST_INSERT_NOPS_4
|
||||
#define TEST_INSERT_NOPS_6 nop; TEST_INSERT_NOPS_5
|
||||
#define TEST_INSERT_NOPS_7 nop; TEST_INSERT_NOPS_6
|
||||
#define TEST_INSERT_NOPS_8 nop; TEST_INSERT_NOPS_7
|
||||
#define TEST_INSERT_NOPS_9 nop; TEST_INSERT_NOPS_8
|
||||
#define TEST_INSERT_NOPS_10 nop; TEST_INSERT_NOPS_9
|
||||
|
||||
#if __riscv_xlen == 64
|
||||
#define LOAD_PTR ld
|
||||
#define STORE_PTR sd
|
||||
#else
|
||||
#define LOAD_PTR lw
|
||||
#define STORE_PTR sw
|
||||
#endif
|
||||
|
||||
#-----------------------------------------------------------------------
|
||||
# RV64UI MACROS
|
||||
#-----------------------------------------------------------------------
|
||||
|
||||
#-----------------------------------------------------------------------
|
||||
# Tests for instructions with immediate operand
|
||||
#-----------------------------------------------------------------------
|
||||
|
||||
#define SEXT_IMM(x) ((x) | (-(((x) >> 11) & 1) << 11))
|
||||
|
||||
#define TEST_IMM_OP( testnum, inst, result, val1, imm ) \
|
||||
TEST_CASE( testnum, x14, result, \
|
||||
li x13, MASK_XLEN(val1); \
|
||||
inst x14, x13, SEXT_IMM(imm); \
|
||||
)
|
||||
|
||||
#define TEST_IMM_SRC1_EQ_DEST( testnum, inst, result, val1, imm ) \
|
||||
TEST_CASE( testnum, x11, result, \
|
||||
li x11, MASK_XLEN(val1); \
|
||||
inst x11, x11, SEXT_IMM(imm); \
|
||||
)
|
||||
|
||||
#define TEST_IMM_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \
|
||||
TEST_CASE( testnum, x6, result, \
|
||||
li x4, 0; \
|
||||
1: li x1, MASK_XLEN(val1); \
|
||||
inst x14, x1, SEXT_IMM(imm); \
|
||||
TEST_INSERT_NOPS_ ## nop_cycles \
|
||||
addi x6, x14, 0; \
|
||||
addi x4, x4, 1; \
|
||||
li x5, 2; \
|
||||
bne x4, x5, 1b \
|
||||
)
|
||||
|
||||
#define TEST_IMM_SRC1_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \
|
||||
TEST_CASE( testnum, x14, result, \
|
||||
li x4, 0; \
|
||||
1: li x1, MASK_XLEN(val1); \
|
||||
TEST_INSERT_NOPS_ ## nop_cycles \
|
||||
inst x14, x1, SEXT_IMM(imm); \
|
||||
addi x4, x4, 1; \
|
||||
li x5, 2; \
|
||||
bne x4, x5, 1b \
|
||||
)
|
||||
|
||||
#define TEST_IMM_ZEROSRC1( testnum, inst, result, imm ) \
|
||||
TEST_CASE( testnum, x1, result, \
|
||||
inst x1, x0, SEXT_IMM(imm); \
|
||||
)
|
||||
|
||||
#define TEST_IMM_ZERODEST( testnum, inst, val1, imm ) \
|
||||
TEST_CASE( testnum, x0, 0, \
|
||||
li x1, MASK_XLEN(val1); \
|
||||
inst x0, x1, SEXT_IMM(imm); \
|
||||
)
|
||||
|
||||
#-----------------------------------------------------------------------
|
||||
# Tests for an instruction with register operands
|
||||
#-----------------------------------------------------------------------
|
||||
|
||||
#define TEST_R_OP( testnum, inst, result, val1 ) \
|
||||
TEST_CASE( testnum, x14, result, \
|
||||
li x1, val1; \
|
||||
inst x14, x1; \
|
||||
)
|
||||
|
||||
#define TEST_R_SRC1_EQ_DEST( testnum, inst, result, val1 ) \
|
||||
TEST_CASE( testnum, x1, result, \
|
||||
li x1, val1; \
|
||||
inst x1, x1; \
|
||||
)
|
||||
|
||||
#define TEST_R_DEST_BYPASS( testnum, nop_cycles, inst, result, val1 ) \
|
||||
TEST_CASE( testnum, x6, result, \
|
||||
li x4, 0; \
|
||||
1: li x1, val1; \
|
||||
inst x14, x1; \
|
||||
TEST_INSERT_NOPS_ ## nop_cycles \
|
||||
addi x6, x14, 0; \
|
||||
addi x4, x4, 1; \
|
||||
li x5, 2; \
|
||||
bne x4, x5, 1b \
|
||||
)
|
||||
|
||||
#-----------------------------------------------------------------------
|
||||
# Tests for an instruction with register-register operands
|
||||
#-----------------------------------------------------------------------
|
||||
|
||||
#define TEST_RR_OP( testnum, inst, result, val1, val2 ) \
|
||||
TEST_CASE( testnum, x14, result, \
|
||||
li x11, MASK_XLEN(val1); \
|
||||
li x12, MASK_XLEN(val2); \
|
||||
inst x14, x11, x12; \
|
||||
)
|
||||
|
||||
#define TEST_RR_SRC1_EQ_DEST( testnum, inst, result, val1, val2 ) \
|
||||
TEST_CASE( testnum, x11, result, \
|
||||
li x11, MASK_XLEN(val1); \
|
||||
li x12, MASK_XLEN(val2); \
|
||||
inst x11, x11, x12; \
|
||||
)
|
||||
|
||||
#define TEST_RR_SRC2_EQ_DEST( testnum, inst, result, val1, val2 ) \
|
||||
TEST_CASE( testnum, x12, result, \
|
||||
li x11, MASK_XLEN(val1); \
|
||||
li x12, MASK_XLEN(val2); \
|
||||
inst x12, x11, x12; \
|
||||
)
|
||||
|
||||
#define TEST_RR_SRC12_EQ_DEST( testnum, inst, result, val1 ) \
|
||||
TEST_CASE( testnum, x11, result, \
|
||||
li x11, MASK_XLEN(val1); \
|
||||
inst x11, x11, x11; \
|
||||
)
|
||||
|
||||
#define TEST_RR_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, val2 ) \
|
||||
TEST_CASE( testnum, x6, result, \
|
||||
li x4, 0; \
|
||||
1: li x1, MASK_XLEN(val1); \
|
||||
li x2, MASK_XLEN(val2); \
|
||||
inst x14, x1, x2; \
|
||||
TEST_INSERT_NOPS_ ## nop_cycles \
|
||||
addi x6, x14, 0; \
|
||||
addi x4, x4, 1; \
|
||||
li x5, 2; \
|
||||
bne x4, x5, 1b \
|
||||
)
|
||||
|
||||
#define TEST_RR_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \
|
||||
TEST_CASE( testnum, x14, result, \
|
||||
li x4, 0; \
|
||||
1: li x1, MASK_XLEN(val1); \
|
||||
TEST_INSERT_NOPS_ ## src1_nops \
|
||||
li x2, MASK_XLEN(val2); \
|
||||
TEST_INSERT_NOPS_ ## src2_nops \
|
||||
inst x14, x1, x2; \
|
||||
addi x4, x4, 1; \
|
||||
li x5, 2; \
|
||||
bne x4, x5, 1b \
|
||||
)
|
||||
|
||||
#define TEST_RR_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \
|
||||
TEST_CASE( testnum, x14, result, \
|
||||
li x4, 0; \
|
||||
1: li x2, MASK_XLEN(val2); \
|
||||
TEST_INSERT_NOPS_ ## src1_nops \
|
||||
li x1, MASK_XLEN(val1); \
|
||||
TEST_INSERT_NOPS_ ## src2_nops \
|
||||
inst x14, x1, x2; \
|
||||
addi x4, x4, 1; \
|
||||
li x5, 2; \
|
||||
bne x4, x5, 1b \
|
||||
)
|
||||
|
||||
#define TEST_RR_ZEROSRC1( testnum, inst, result, val ) \
|
||||
TEST_CASE( testnum, x2, result, \
|
||||
li x1, MASK_XLEN(val); \
|
||||
inst x2, x0, x1; \
|
||||
)
|
||||
|
||||
#define TEST_RR_ZEROSRC2( testnum, inst, result, val ) \
|
||||
TEST_CASE( testnum, x2, result, \
|
||||
li x1, MASK_XLEN(val); \
|
||||
inst x2, x1, x0; \
|
||||
)
|
||||
|
||||
#define TEST_RR_ZEROSRC12( testnum, inst, result ) \
|
||||
TEST_CASE( testnum, x1, result, \
|
||||
inst x1, x0, x0; \
|
||||
)
|
||||
|
||||
#define TEST_RR_ZERODEST( testnum, inst, val1, val2 ) \
|
||||
TEST_CASE( testnum, x0, 0, \
|
||||
li x1, MASK_XLEN(val1); \
|
||||
li x2, MASK_XLEN(val2); \
|
||||
inst x0, x1, x2; \
|
||||
)
|
||||
|
||||
#-----------------------------------------------------------------------
|
||||
# Test memory instructions
|
||||
#-----------------------------------------------------------------------
|
||||
|
||||
#define TEST_LD_OP( testnum, inst, result, offset, base ) \
|
||||
TEST_CASE( testnum, x14, result, \
|
||||
li x15, result; /* Tell the exception handler the expected result. */ \
|
||||
la x2, base; \
|
||||
inst x14, offset(x2); \
|
||||
)
|
||||
|
||||
#define TEST_ST_OP( testnum, load_inst, store_inst, result, offset, base ) \
|
||||
TEST_CASE( testnum, x14, result, \
|
||||
la x2, base; \
|
||||
li x1, result; \
|
||||
la x15, 7f; /* Tell the exception handler how to skip this test. */ \
|
||||
store_inst x1, offset(x2); \
|
||||
load_inst x14, offset(x2); \
|
||||
j 8f; \
|
||||
7: \
|
||||
/* Set up the correct result for TEST_CASE(). */ \
|
||||
mv x14, x1; \
|
||||
8: \
|
||||
)
|
||||
|
||||
#define TEST_LD_DEST_BYPASS( testnum, nop_cycles, inst, result, offset, base ) \
|
||||
test_ ## testnum: \
|
||||
li TESTNUM, testnum; \
|
||||
li x4, 0; \
|
||||
1: la x13, base; \
|
||||
inst x14, offset(x13); \
|
||||
TEST_INSERT_NOPS_ ## nop_cycles \
|
||||
addi x6, x14, 0; \
|
||||
li x7, result; \
|
||||
bne x6, x7, fail; \
|
||||
addi x4, x4, 1; \
|
||||
li x5, 2; \
|
||||
bne x4, x5, 1b; \
|
||||
|
||||
#define TEST_LD_SRC1_BYPASS( testnum, nop_cycles, inst, result, offset, base ) \
|
||||
test_ ## testnum: \
|
||||
li TESTNUM, testnum; \
|
||||
li x4, 0; \
|
||||
1: la x13, base; \
|
||||
TEST_INSERT_NOPS_ ## nop_cycles \
|
||||
inst x14, offset(x13); \
|
||||
li x7, result; \
|
||||
bne x14, x7, fail; \
|
||||
addi x4, x4, 1; \
|
||||
li x5, 2; \
|
||||
bne x4, x5, 1b \
|
||||
|
||||
#define TEST_ST_SRC12_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \
|
||||
test_ ## testnum: \
|
||||
li TESTNUM, testnum; \
|
||||
li x4, 0; \
|
||||
1: li x13, result; \
|
||||
TEST_INSERT_NOPS_ ## src1_nops \
|
||||
la x12, base; \
|
||||
TEST_INSERT_NOPS_ ## src2_nops \
|
||||
store_inst x13, offset(x12); \
|
||||
load_inst x14, offset(x12); \
|
||||
li x7, result; \
|
||||
bne x14, x7, fail; \
|
||||
addi x4, x4, 1; \
|
||||
li x5, 2; \
|
||||
bne x4, x5, 1b \
|
||||
|
||||
#define TEST_ST_SRC21_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \
|
||||
test_ ## testnum: \
|
||||
li TESTNUM, testnum; \
|
||||
li x4, 0; \
|
||||
1: la x2, base; \
|
||||
TEST_INSERT_NOPS_ ## src1_nops \
|
||||
li x1, result; \
|
||||
TEST_INSERT_NOPS_ ## src2_nops \
|
||||
store_inst x1, offset(x2); \
|
||||
load_inst x14, offset(x2); \
|
||||
li x7, result; \
|
||||
bne x14, x7, fail; \
|
||||
addi x4, x4, 1; \
|
||||
li x5, 2; \
|
||||
bne x4, x5, 1b \
|
||||
|
||||
#define TEST_LD_ST_BYPASS(testnum, load_inst, store_inst, result, offset, base) \
|
||||
test_ ## testnum: \
|
||||
li TESTNUM, testnum; \
|
||||
la x2, base; \
|
||||
li x1, result; \
|
||||
store_inst x1, offset(x2); \
|
||||
load_inst x14, offset(x2); \
|
||||
store_inst x14, offset(x2); \
|
||||
load_inst x2, offset(x2); \
|
||||
li x7, result; \
|
||||
bne x2, x7, fail; \
|
||||
la x2, base; \
|
||||
STORE_PTR x2,8(x2); \
|
||||
LOAD_PTR x4,8(x2); \
|
||||
store_inst x1, offset(x4); \
|
||||
bne x4, x2, fail; \
|
||||
load_inst x14, offset(x4); \
|
||||
bne x14, x7, fail; \
|
||||
|
||||
#define TEST_ST_LD_BYPASS(testnum, load_inst, store_inst, result, offset, base) \
|
||||
test_ ## testnum: \
|
||||
li TESTNUM, testnum; \
|
||||
la x2, base; \
|
||||
li x1, result; \
|
||||
store_inst x1, offset(x2); \
|
||||
load_inst x14, offset(x2); \
|
||||
li x7, result; \
|
||||
bne x14, x7, fail; \
|
||||
|
||||
#define TEST_BR2_OP_TAKEN(testnum, inst, val1, val2 ) \
|
||||
test_ ## testnum: \
|
||||
li TESTNUM, testnum; \
|
||||
li x1, val1; \
|
||||
li x2, val2; \
|
||||
inst x1, x2, 2f; \
|
||||
bne x0, TESTNUM, fail; \
|
||||
1: bne x0, TESTNUM, 3f; \
|
||||
2: inst x1, x2, 1b; \
|
||||
bne x0, TESTNUM, fail; \
|
||||
3:
|
||||
|
||||
#define TEST_BR2_OP_NOTTAKEN( testnum, inst, val1, val2 ) \
|
||||
test_ ## testnum: \
|
||||
li TESTNUM, testnum; \
|
||||
li x1, val1; \
|
||||
li x2, val2; \
|
||||
inst x1, x2, 1f; \
|
||||
bne x0, TESTNUM, 2f; \
|
||||
1: bne x0, TESTNUM, fail; \
|
||||
2: inst x1, x2, 1b; \
|
||||
3:
|
||||
|
||||
#define TEST_BR2_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \
|
||||
test_ ## testnum: \
|
||||
li TESTNUM, testnum; \
|
||||
li x4, 0; \
|
||||
1: li x1, val1; \
|
||||
TEST_INSERT_NOPS_ ## src1_nops \
|
||||
li x2, val2; \
|
||||
TEST_INSERT_NOPS_ ## src2_nops \
|
||||
inst x1, x2, fail; \
|
||||
addi x4, x4, 1; \
|
||||
li x5, 2; \
|
||||
bne x4, x5, 1b \
|
||||
|
||||
#define TEST_BR2_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \
|
||||
test_ ## testnum: \
|
||||
li TESTNUM, testnum; \
|
||||
li x4, 0; \
|
||||
1: li x2, val2; \
|
||||
TEST_INSERT_NOPS_ ## src1_nops \
|
||||
li x1, val1; \
|
||||
TEST_INSERT_NOPS_ ## src2_nops \
|
||||
inst x1, x2, fail; \
|
||||
addi x4, x4, 1; \
|
||||
li x5, 2; \
|
||||
bne x4, x5, 1b \
|
||||
|
||||
#-----------------------------------------------------------------------
|
||||
# Test jump instructions
|
||||
#-----------------------------------------------------------------------
|
||||
|
||||
#define TEST_JR_SRC1_BYPASS( testnum, nop_cycles, inst ) \
|
||||
test_ ## testnum: \
|
||||
li TESTNUM, testnum; \
|
||||
li x4, 0; \
|
||||
1: la x6, 2f; \
|
||||
TEST_INSERT_NOPS_ ## nop_cycles \
|
||||
inst x6; \
|
||||
bne x0, TESTNUM, fail; \
|
||||
2: addi x4, x4, 1; \
|
||||
li x5, 2; \
|
||||
bne x4, x5, 1b \
|
||||
|
||||
#define TEST_JALR_SRC1_BYPASS( testnum, nop_cycles, inst ) \
|
||||
test_ ## testnum: \
|
||||
li TESTNUM, testnum; \
|
||||
li x4, 0; \
|
||||
1: la x6, 2f; \
|
||||
TEST_INSERT_NOPS_ ## nop_cycles \
|
||||
inst x13, x6, 0; \
|
||||
bne x0, TESTNUM, fail; \
|
||||
2: addi x4, x4, 1; \
|
||||
li x5, 2; \
|
||||
bne x4, x5, 1b \
|
||||
|
||||
|
||||
#-----------------------------------------------------------------------
|
||||
# RV64UF MACROS
|
||||
#-----------------------------------------------------------------------
|
||||
|
||||
#-----------------------------------------------------------------------
|
||||
# Tests floating-point instructions
|
||||
#-----------------------------------------------------------------------
|
||||
|
||||
# 16-bit half precision (float16)
|
||||
#define qNaNh 0x7e00
|
||||
#define sNaNh 0x7c01
|
||||
#define Infh 0x7c00
|
||||
#define nInfh 0xfc00
|
||||
|
||||
# 32-bit single precision (float)
|
||||
#define qNaNf 0x7fc00000
|
||||
#define sNaNf 0x7f800001
|
||||
#define Inff 0x7f800000
|
||||
#define nInff 0xff800000
|
||||
|
||||
# 64-bit double precision (double)
|
||||
#define qNaNd 0x7ff8000000000000
|
||||
#define sNaNd 0x7ff0000000000001
|
||||
#define Infd 0x7ff0000000000000
|
||||
#define nInfd 0xfff0000000000000
|
||||
|
||||
#define TEST_FP_OP_H_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \
|
||||
test_ ## testnum: \
|
||||
li TESTNUM, testnum; \
|
||||
la a0, test_ ## testnum ## _data ;\
|
||||
flh f10, 0(a0); \
|
||||
flh f11, 2(a0); \
|
||||
flh f12, 4(a0); \
|
||||
lh a3, 6(a0); \
|
||||
code; \
|
||||
fsflags a1, x0; \
|
||||
li a2, flags; \
|
||||
bne a0, a3, fail; \
|
||||
bne a1, a2, fail; \
|
||||
.pushsection .data; \
|
||||
.align 1; \
|
||||
test_ ## testnum ## _data: \
|
||||
.val1; \
|
||||
.val2; \
|
||||
.val3; \
|
||||
.result; \
|
||||
.popsection
|
||||
|
||||
#define TEST_FP_OP_S_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \
|
||||
test_ ## testnum: \
|
||||
li TESTNUM, testnum; \
|
||||
la a0, test_ ## testnum ## _data ;\
|
||||
flw f10, 0(a0); \
|
||||
flw f11, 4(a0); \
|
||||
flw f12, 8(a0); \
|
||||
lw a3, 12(a0); \
|
||||
code; \
|
||||
fsflags a1, x0; \
|
||||
li a2, flags; \
|
||||
bne a0, a3, fail; \
|
||||
bne a1, a2, fail; \
|
||||
.pushsection .data; \
|
||||
.align 2; \
|
||||
test_ ## testnum ## _data: \
|
||||
.val1; \
|
||||
.val2; \
|
||||
.val3; \
|
||||
.result; \
|
||||
.popsection
|
||||
|
||||
#define TEST_FP_OP_D_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \
|
||||
test_ ## testnum: \
|
||||
li TESTNUM, testnum; \
|
||||
la a0, test_ ## testnum ## _data ;\
|
||||
fld f10, 0(a0); \
|
||||
fld f11, 8(a0); \
|
||||
fld f12, 16(a0); \
|
||||
ld a3, 24(a0); \
|
||||
code; \
|
||||
fsflags a1, x0; \
|
||||
li a2, flags; \
|
||||
bne a0, a3, fail; \
|
||||
bne a1, a2, fail; \
|
||||
.pushsection .data; \
|
||||
.align 3; \
|
||||
test_ ## testnum ## _data: \
|
||||
.val1; \
|
||||
.val2; \
|
||||
.val3; \
|
||||
.result; \
|
||||
.popsection
|
||||
|
||||
// TODO: assign a separate mem location for the comparison address?
|
||||
#define TEST_FP_OP_D32_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \
|
||||
test_ ## testnum: \
|
||||
li TESTNUM, testnum; \
|
||||
la a0, test_ ## testnum ## _data ;\
|
||||
fld f10, 0(a0); \
|
||||
fld f11, 8(a0); \
|
||||
fld f12, 16(a0); \
|
||||
lw a3, 24(a0); \
|
||||
lw t1, 28(a0); \
|
||||
code; \
|
||||
fsflags a1, x0; \
|
||||
li a2, flags; \
|
||||
bne a0, a3, fail; \
|
||||
bne t1, t2, fail; \
|
||||
bne a1, a2, fail; \
|
||||
.pushsection .data; \
|
||||
.align 3; \
|
||||
test_ ## testnum ## _data: \
|
||||
.val1; \
|
||||
.val2; \
|
||||
.val3; \
|
||||
.result; \
|
||||
.popsection
|
||||
|
||||
#define TEST_FCVT_S_D32( testnum, result, val1 ) \
|
||||
TEST_FP_OP_D32_INTERNAL( testnum, 0, double result, double val1, double 0, double 0, \
|
||||
fcvt.s.d f13, f10; fcvt.d.s f13, f13; fsd f13, 0(a0); lw t2, 4(a0); lw a0, 0(a0))
|
||||
|
||||
#define TEST_FCVT_S_D( testnum, result, val1 ) \
|
||||
TEST_FP_OP_D_INTERNAL( testnum, 0, double result, double val1, double 0, double 0, \
|
||||
fcvt.s.d f13, f10; fcvt.d.s f13, f13; fmv.x.d a0, f13)
|
||||
|
||||
#define TEST_FCVT_D_S( testnum, result, val1 ) \
|
||||
TEST_FP_OP_S_INTERNAL( testnum, 0, float result, float val1, float 0, float 0, \
|
||||
fcvt.d.s f13, f10; fcvt.s.d f13, f13; fmv.x.s a0, f13)
|
||||
|
||||
#define TEST_FCVT_H_S( testnum, result, val1 ) \
|
||||
TEST_FP_OP_H_INTERNAL( testnum, 0, float16 result, float16 val1, float16 0, float16 0, \
|
||||
fcvt.s.h f13, f10; fcvt.h.s f13, f13; fmv.x.h a0, f13)
|
||||
|
||||
#define TEST_FCVT_H_D( testnum, result, val1 ) \
|
||||
TEST_FP_OP_H_INTERNAL( testnum, 0, float16 result, float16 val1, float16 0, float16 0, \
|
||||
fcvt.d.h f13, f10; fcvt.h.d f13, f13; fmv.x.h a0, f13)
|
||||
|
||||
|
||||
#define TEST_FP_OP1_H( testnum, inst, flags, result, val1 ) \
|
||||
TEST_FP_OP_H_INTERNAL( testnum, flags, float16 result, float16 val1, float16 0, float16 0, \
|
||||
inst f13, f10; fmv.x.h a0, f13;)
|
||||
|
||||
#define TEST_FP_OP1_S( testnum, inst, flags, result, val1 ) \
|
||||
TEST_FP_OP_S_INTERNAL( testnum, flags, float result, float val1, float 0, float 0, \
|
||||
inst f13, f10; fmv.x.s a0, f13)
|
||||
|
||||
#define TEST_FP_OP1_D32( testnum, inst, flags, result, val1 ) \
|
||||
TEST_FP_OP_D32_INTERNAL( testnum, flags, double result, double val1, double 0, double 0, \
|
||||
inst f13, f10; fsd f13, 0(a0); lw t2, 4(a0); lw a0, 0(a0))
|
||||
// ^: store computation result in address from a0, load high-word into t2
|
||||
|
||||
#define TEST_FP_OP1_D( testnum, inst, flags, result, val1 ) \
|
||||
TEST_FP_OP_D_INTERNAL( testnum, flags, double result, double val1, double 0, double 0, \
|
||||
inst f13, f10; fmv.x.d a0, f13)
|
||||
|
||||
#define TEST_FP_OP1_S_DWORD_RESULT( testnum, inst, flags, result, val1 ) \
|
||||
TEST_FP_OP_S_INTERNAL( testnum, flags, dword result, float val1, float 0, float 0, \
|
||||
inst f13, f10; fmv.x.s a0, f13)
|
||||
|
||||
#define TEST_FP_OP1_H_DWORD_RESULT( testnum, inst, flags, result, val1 ) \
|
||||
TEST_FP_OP_H_INTERNAL( testnum, flags, word result, float16 val1, float16 0, float16 0, \
|
||||
inst f13, f10; fmv.x.h a0, f13)
|
||||
|
||||
#define TEST_FP_OP1_D32_DWORD_RESULT( testnum, inst, flags, result, val1 ) \
|
||||
TEST_FP_OP_D32_INTERNAL( testnum, flags, dword result, double val1, double 0, double 0, \
|
||||
inst f13, f10; fsd f13, 0(a0); lw t2, 4(a0); lw a0, 0(a0))
|
||||
// ^: store computation result in address from a0, load high-word into t2
|
||||
|
||||
#define TEST_FP_OP1_D_DWORD_RESULT( testnum, inst, flags, result, val1 ) \
|
||||
TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, double val1, double 0, double 0, \
|
||||
inst f13, f10; fmv.x.d a0, f13)
|
||||
|
||||
#define TEST_FP_OP2_S( testnum, inst, flags, result, val1, val2 ) \
|
||||
TEST_FP_OP_S_INTERNAL( testnum, flags, float result, float val1, float val2, float 0, \
|
||||
inst f13, f10, f11; fmv.x.s a0, f13)
|
||||
|
||||
#define TEST_FP_OP2_S_HEX( testnum, inst, flags, result, val1, val2 ) \
|
||||
TEST_FP_OP_S_INTERNAL( testnum, flags, word result, word val1, word val2, float 0, \
|
||||
inst f13, f10, f11; fmv.x.s a0, f13)
|
||||
|
||||
#define TEST_FP_OP2_H( testnum, inst, flags, result, val1, val2 ) \
|
||||
TEST_FP_OP_H_INTERNAL( testnum, flags, float16 result, float16 val1, float16 val2, float16 0, \
|
||||
inst f13, f10, f11; fmv.x.h a0, f13)
|
||||
|
||||
#define TEST_FP_OP2_H_HEX( testnum, inst, flags, result, val1, val2 ) \
|
||||
TEST_FP_OP_H_INTERNAL( testnum, flags, half result, half val1, half val2, float16 0, \
|
||||
inst f13, f10, f11; fmv.x.h a0, f13)
|
||||
|
||||
#define TEST_FP_OP2_D32( testnum, inst, flags, result, val1, val2 ) \
|
||||
TEST_FP_OP_D32_INTERNAL( testnum, flags, double result, double val1, double val2, double 0, \
|
||||
inst f13, f10, f11; fsd f13, 0(a0); lw t2, 4(a0); lw a0, 0(a0))
|
||||
// ^: store computation result in address from a0, load high-word into t2
|
||||
|
||||
#define TEST_FP_OP2_D32_HEX( testnum, inst, flags, result, val1, val2 ) \
|
||||
TEST_FP_OP_D32_INTERNAL( testnum, flags, dword result, dword val1, dword val2, double 0, \
|
||||
inst f13, f10, f11; fsd f13, 0(a0); lw t2, 4(a0); lw a0, 0(a0))
|
||||
|
||||
#define TEST_FP_OP2_D( testnum, inst, flags, result, val1, val2 ) \
|
||||
TEST_FP_OP_D_INTERNAL( testnum, flags, double result, double val1, double val2, double 0, \
|
||||
inst f13, f10, f11; fmv.x.d a0, f13)
|
||||
|
||||
#define TEST_FP_OP2_D_HEX( testnum, inst, flags, result, val1, val2 ) \
|
||||
TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, dword val1, dword val2, double 0, \
|
||||
inst f13, f10, f11; fmv.x.d a0, f13)
|
||||
|
||||
#define TEST_FP_OP3_S( testnum, inst, flags, result, val1, val2, val3 ) \
|
||||
TEST_FP_OP_S_INTERNAL( testnum, flags, float result, float val1, float val2, float val3, \
|
||||
inst f13, f10, f11, f12; fmv.x.s a0, f13)
|
||||
|
||||
#define TEST_FP_OP3_H( testnum, inst, flags, result, val1, val2, val3 ) \
|
||||
TEST_FP_OP_H_INTERNAL( testnum, flags, float16 result, float16 val1, float16 val2, float16 val3, \
|
||||
inst f13, f10, f11, f12; fmv.x.h a0, f13)
|
||||
|
||||
#define TEST_FP_OP3_D32( testnum, inst, flags, result, val1, val2, val3 ) \
|
||||
TEST_FP_OP_D32_INTERNAL( testnum, flags, double result, double val1, double val2, double val3, \
|
||||
inst f13, f10, f11, f12; fsd f13, 0(a0); lw t2, 4(a0); lw a0, 0(a0))
|
||||
// ^: store computation result in address from a0, load high-word into t2
|
||||
|
||||
#define TEST_FP_OP3_D( testnum, inst, flags, result, val1, val2, val3 ) \
|
||||
TEST_FP_OP_D_INTERNAL( testnum, flags, double result, double val1, double val2, double val3, \
|
||||
inst f13, f10, f11, f12; fmv.x.d a0, f13)
|
||||
|
||||
#define TEST_FP_INT_OP_S( testnum, inst, flags, result, val1, rm ) \
|
||||
TEST_FP_OP_S_INTERNAL( testnum, flags, word result, float val1, float 0, float 0, \
|
||||
inst a0, f10, rm)
|
||||
|
||||
#define TEST_FP_INT_OP_H( testnum, inst, flags, result, val1, rm ) \
|
||||
TEST_FP_OP_H_INTERNAL( testnum, flags, word result, float16 val1, float16 0, float16 0, \
|
||||
inst a0, f10, rm)
|
||||
|
||||
#define TEST_FP_INT_OP_D32( testnum, inst, flags, result, val1, rm ) \
|
||||
TEST_FP_OP_D32_INTERNAL( testnum, flags, dword result, double val1, double 0, double 0, \
|
||||
inst a0, f10, rm; li t2, ((result) << 32 >> 63) * -1)
|
||||
|
||||
#define TEST_FP_INT_OP_D( testnum, inst, flags, result, val1, rm ) \
|
||||
TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, double val1, double 0, double 0, \
|
||||
inst a0, f10, rm)
|
||||
|
||||
#define TEST_FP_CMP_OP_S( testnum, inst, flags, result, val1, val2 ) \
|
||||
TEST_FP_OP_S_INTERNAL( testnum, flags, word result, float val1, float val2, float 0, \
|
||||
inst a0, f10, f11)
|
||||
|
||||
#define TEST_FP_CMP_OP_S_HEX( testnum, inst, flags, result, val1, val2 ) \
|
||||
TEST_FP_OP_S_INTERNAL( testnum, flags, word result, word val1, word val2, float 0, \
|
||||
inst a0, f10, f11)
|
||||
|
||||
#define TEST_FP_CMP_OP_H( testnum, inst, flags, result, val1, val2 ) \
|
||||
TEST_FP_OP_H_INTERNAL( testnum, flags, hword result, float16 val1, float16 val2, float16 0, \
|
||||
inst a0, f10, f11)
|
||||
|
||||
#define TEST_FP_CMP_OP_H_HEX( testnum, inst, flags, result, val1, val2 ) \
|
||||
TEST_FP_OP_H_INTERNAL( testnum, flags, hword result, half val1, half val2, float16 0, \
|
||||
inst a0, f10, f11)
|
||||
|
||||
#define TEST_FP_CMP_OP_D32( testnum, inst, flags, result, val1, val2 ) \
|
||||
TEST_FP_OP_D32_INTERNAL( testnum, flags, dword result, double val1, double val2, double 0, \
|
||||
inst a0, f10, f11; li t2, 0)
|
||||
|
||||
#define TEST_FP_CMP_OP_D32_HEX( testnum, inst, flags, result, val1, val2 ) \
|
||||
TEST_FP_OP_D32_INTERNAL( testnum, flags, dword result, dword val1, dword val2, double 0, \
|
||||
inst a0, f10, f11; li t2, 0)
|
||||
|
||||
#define TEST_FP_CMP_OP_D( testnum, inst, flags, result, val1, val2 ) \
|
||||
TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, double val1, double val2, double 0, \
|
||||
inst a0, f10, f11)
|
||||
|
||||
#define TEST_FP_CMP_OP_D_HEX( testnum, inst, flags, result, val1, val2 ) \
|
||||
TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, dword val1, dword val2, double 0, \
|
||||
inst a0, f10, f11)
|
||||
|
||||
#define TEST_FCLASS_S(testnum, correct, input) \
|
||||
TEST_CASE(testnum, a0, correct, li a0, input; fmv.s.x f10, a0; \
|
||||
fclass.s a0, f10)
|
||||
|
||||
#define TEST_FCLASS_D32(testnum, correct, input) \
|
||||
TEST_CASE(testnum, a0, correct, \
|
||||
la a0, test_ ## testnum ## _data ;\
|
||||
fld f10, 0(a0); \
|
||||
fclass.d a0, f10) \
|
||||
.pushsection .data; \
|
||||
.align 3; \
|
||||
test_ ## testnum ## _data: \
|
||||
.dword input; \
|
||||
.popsection
|
||||
|
||||
#define TEST_FCLASS_D(testnum, correct, input) \
|
||||
TEST_CASE(testnum, a0, correct, li a0, input; fmv.d.x f10, a0; \
|
||||
fclass.d a0, f10)
|
||||
|
||||
#define TEST_INT_FP_OP_S( testnum, inst, result, val1 ) \
|
||||
test_ ## testnum: \
|
||||
li TESTNUM, testnum; \
|
||||
la a0, test_ ## testnum ## _data ;\
|
||||
lw a3, 0(a0); \
|
||||
li a0, val1; \
|
||||
inst f10, a0; \
|
||||
fsflags x0; \
|
||||
fmv.x.s a0, f10; \
|
||||
bne a0, a3, fail; \
|
||||
.pushsection .data; \
|
||||
.align 2; \
|
||||
test_ ## testnum ## _data: \
|
||||
.float result; \
|
||||
.popsection
|
||||
|
||||
#define TEST_INT_FP_OP_H( testnum, inst, result, val1 ) \
|
||||
test_ ## testnum: \
|
||||
li TESTNUM, testnum; \
|
||||
la a0, test_ ## testnum ## _data ;\
|
||||
lh a3, 0(a0); \
|
||||
li a0, val1; \
|
||||
inst f10, a0; \
|
||||
fsflags x0; \
|
||||
fmv.x.h a0, f10; \
|
||||
bne a0, a3, fail; \
|
||||
.pushsection .data; \
|
||||
.align 1; \
|
||||
test_ ## testnum ## _data: \
|
||||
.float16 result; \
|
||||
.popsection
|
||||
|
||||
#define TEST_INT_FP_OP_D32( testnum, inst, result, val1 ) \
|
||||
test_ ## testnum: \
|
||||
li TESTNUM, testnum; \
|
||||
la a0, test_ ## testnum ## _data ;\
|
||||
lw a3, 0(a0); \
|
||||
lw a4, 4(a0); \
|
||||
li a1, val1; \
|
||||
inst f10, a1; \
|
||||
\
|
||||
fsd f10, 0(a0); \
|
||||
lw a1, 4(a0); \
|
||||
lw a0, 0(a0); \
|
||||
\
|
||||
fsflags x0; \
|
||||
bne a0, a3, fail; \
|
||||
bne a1, a4, fail; \
|
||||
.pushsection .data; \
|
||||
.align 3; \
|
||||
test_ ## testnum ## _data: \
|
||||
.double result; \
|
||||
.popsection
|
||||
|
||||
#define TEST_INT_FP_OP_D( testnum, inst, result, val1 ) \
|
||||
test_ ## testnum: \
|
||||
li TESTNUM, testnum; \
|
||||
la a0, test_ ## testnum ## _data ;\
|
||||
ld a3, 0(a0); \
|
||||
li a0, val1; \
|
||||
inst f10, a0; \
|
||||
fsflags x0; \
|
||||
fmv.x.d a0, f10; \
|
||||
bne a0, a3, fail; \
|
||||
.pushsection .data; \
|
||||
.align 3; \
|
||||
test_ ## testnum ## _data: \
|
||||
.double result; \
|
||||
.popsection
|
||||
|
||||
// We need some special handling here to allow 64-bit comparison in 32-bit arch
|
||||
// TODO: find a better name and clean up when intended for general usage?
|
||||
#define TEST_CASE_D32( testnum, testreg1, testreg2, correctval, code... ) \
|
||||
test_ ## testnum: \
|
||||
code; \
|
||||
la x15, test_ ## testnum ## _data ; \
|
||||
lw x7, 0(x15); \
|
||||
lw x15, 4(x15); \
|
||||
li TESTNUM, testnum; \
|
||||
bne testreg1, x7, fail;\
|
||||
bne testreg2, x15, fail;\
|
||||
.pushsection .data; \
|
||||
.align 3; \
|
||||
test_ ## testnum ## _data: \
|
||||
.dword correctval; \
|
||||
.popsection
|
||||
|
||||
// ^ x14 is used in some other macros, to avoid issues we use x15 for upper word
|
||||
|
||||
#define MISALIGNED_LOAD_HANDLER \
|
||||
li t0, CAUSE_MISALIGNED_LOAD; \
|
||||
csrr t1, mcause; \
|
||||
bne t0, t1, fail; \
|
||||
\
|
||||
/* We got a misaligned exception. Pretend we handled it in software */ \
|
||||
/* by loading the correct result here. */ \
|
||||
mv a4, a5; \
|
||||
\
|
||||
/* And skip this instruction */ \
|
||||
csrr t0, mepc; \
|
||||
addi t0, t0, 4; \
|
||||
csrw mepc, t0; \
|
||||
mret
|
||||
|
||||
#define MISALIGNED_STORE_HANDLER \
|
||||
li t0, CAUSE_MISALIGNED_STORE; \
|
||||
csrr t1, mcause; \
|
||||
bne t0, t1, fail; \
|
||||
\
|
||||
/* We got a misaligned exception. Skip this test. */ \
|
||||
csrw mepc, x15; \
|
||||
mret
|
||||
|
||||
#-----------------------------------------------------------------------
|
||||
# Pass and fail code (assumes test num is in TESTNUM)
|
||||
#-----------------------------------------------------------------------
|
||||
|
||||
#define TEST_PASSFAIL \
|
||||
bne x0, TESTNUM, pass; \
|
||||
fail: \
|
||||
RVTEST_FAIL; \
|
||||
pass: \
|
||||
RVTEST_PASS \
|
||||
|
||||
|
||||
#-----------------------------------------------------------------------
|
||||
# Test data section
|
||||
#-----------------------------------------------------------------------
|
||||
|
||||
#define TEST_DATA
|
||||
|
||||
#endif
|
||||
331
Tests/isa/Cprograms/vm.c
Normal file
331
Tests/isa/Cprograms/vm.c
Normal file
@@ -0,0 +1,331 @@
|
||||
// See LICENSE for license details.
|
||||
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
#include <stdio.h>
|
||||
|
||||
#include "riscv_test.h"
|
||||
|
||||
#define SYS_write 64
|
||||
|
||||
#if __riscv_xlen == 32
|
||||
# define SATP_MODE_CHOICE SATP_MODE_SV32
|
||||
#elif defined(Sv48)
|
||||
# define SATP_MODE_CHOICE SATP_MODE_SV48
|
||||
#else
|
||||
# define SATP_MODE_CHOICE SATP_MODE_SV39
|
||||
#endif
|
||||
|
||||
void trap_entry();
|
||||
void pop_tf(trapframe_t*);
|
||||
|
||||
extern volatile uint64_t tohost;
|
||||
extern volatile uint64_t fromhost;
|
||||
|
||||
static void do_tohost(uint64_t tohost_value)
|
||||
{
|
||||
while (tohost)
|
||||
fromhost = 0;
|
||||
tohost = tohost_value;
|
||||
}
|
||||
|
||||
#define pa2kva(pa) ((void*)(pa) - DRAM_BASE - MEGAPAGE_SIZE)
|
||||
#define uva2kva(pa) ((void*)(pa) - MEGAPAGE_SIZE)
|
||||
|
||||
#define flush_page(addr) asm volatile ("sfence.vma %0" : : "r" (addr) : "memory")
|
||||
|
||||
static uint64_t lfsr63(uint64_t x)
|
||||
{
|
||||
uint64_t bit = (x ^ (x >> 1)) & 1;
|
||||
return (x >> 1) | (bit << 62);
|
||||
}
|
||||
|
||||
static void cputchar(int x)
|
||||
{
|
||||
#if __riscv_xlen == 32
|
||||
// HTIF devices are not supported on RV32, so proxy a write system call
|
||||
volatile uint64_t syscall_struct[8];
|
||||
volatile int buff = x;
|
||||
syscall_struct[0] = SYS_write;
|
||||
syscall_struct[1] = 1;
|
||||
syscall_struct[2] = (uintptr_t)&buff;
|
||||
syscall_struct[3] = 1;
|
||||
do_tohost((uintptr_t)&syscall_struct);
|
||||
// Wait for response as struct has to be read by HTIF
|
||||
while(!fromhost);
|
||||
#else
|
||||
do_tohost(0x0101000000000000 | (unsigned char)x);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void cputstring(const char* s)
|
||||
{
|
||||
while (*s)
|
||||
cputchar(*s++);
|
||||
}
|
||||
|
||||
static void terminate(int code)
|
||||
{
|
||||
do_tohost(code);
|
||||
while (1);
|
||||
}
|
||||
|
||||
void wtf()
|
||||
{
|
||||
terminate(841);
|
||||
}
|
||||
|
||||
#define stringify1(x) #x
|
||||
#define stringify(x) stringify1(x)
|
||||
#define assert(x) do { \
|
||||
if (x) break; \
|
||||
cputstring("Assertion failed: " stringify(x) "\n"); \
|
||||
terminate(3); \
|
||||
} while(0)
|
||||
|
||||
#define l1pt pt[0]
|
||||
#define user_l2pt pt[1]
|
||||
#if SATP_MODE_CHOICE == SATP_MODE_SV48
|
||||
# define NPT 6
|
||||
# define kernel_l2pt pt[2]
|
||||
# define kernel_l3pt pt[3]
|
||||
# define user_l3pt pt[4]
|
||||
# define user_llpt pt[5]
|
||||
#elif SATP_MODE_CHOICE == SATP_MODE_SV39
|
||||
# define NPT 4
|
||||
# define kernel_l2pt pt[2]
|
||||
# define user_llpt pt[3]
|
||||
#elif SATP_MODE_CHOICE == SATP_MODE_SV32
|
||||
# define NPT 2
|
||||
# define user_llpt user_l2pt
|
||||
#else
|
||||
# error Unknown SATP_MODE_CHOICE
|
||||
#endif
|
||||
pte_t pt[NPT][PTES_PER_PT] __attribute__((aligned(PGSIZE)));
|
||||
|
||||
typedef struct { pte_t addr; void* next; } freelist_t;
|
||||
|
||||
freelist_t user_mapping[MAX_TEST_PAGES];
|
||||
freelist_t freelist_nodes[MAX_TEST_PAGES];
|
||||
freelist_t *freelist_head, *freelist_tail;
|
||||
|
||||
void printhex(uint64_t x)
|
||||
{
|
||||
char str[17];
|
||||
for (int i = 0; i < 16; i++)
|
||||
{
|
||||
str[15-i] = (x & 0xF) + ((x & 0xF) < 10 ? '0' : 'a'-10);
|
||||
x >>= 4;
|
||||
}
|
||||
str[16] = 0;
|
||||
|
||||
cputstring(str);
|
||||
}
|
||||
|
||||
static void evict(unsigned long addr)
|
||||
{
|
||||
assert(addr >= PGSIZE && addr < MAX_TEST_PAGES * PGSIZE);
|
||||
addr = addr/PGSIZE*PGSIZE;
|
||||
|
||||
freelist_t* node = &user_mapping[addr/PGSIZE];
|
||||
if (node->addr)
|
||||
{
|
||||
// check accessed and dirty bits
|
||||
assert(user_llpt[addr/PGSIZE] & PTE_A);
|
||||
uintptr_t sstatus = set_csr(sstatus, SSTATUS_SUM);
|
||||
if (memcmp((void*)addr, uva2kva(addr), PGSIZE)) {
|
||||
assert(user_llpt[addr/PGSIZE] & PTE_D);
|
||||
memcpy(uva2kva(addr), (void*)addr, PGSIZE);
|
||||
}
|
||||
write_csr(sstatus, sstatus);
|
||||
|
||||
user_mapping[addr/PGSIZE].addr = 0;
|
||||
|
||||
if (freelist_tail == 0)
|
||||
freelist_head = freelist_tail = node;
|
||||
else
|
||||
{
|
||||
freelist_tail->next = node;
|
||||
freelist_tail = node;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
extern int pf_filter(uintptr_t addr, uintptr_t *pte, int *copy);
|
||||
extern int trap_filter(trapframe_t *tf);
|
||||
|
||||
void handle_fault(uintptr_t addr, uintptr_t cause)
|
||||
{
|
||||
uintptr_t filter_encodings = 0;
|
||||
int copy_page = 1;
|
||||
|
||||
assert(addr >= PGSIZE && addr < MAX_TEST_PAGES * PGSIZE);
|
||||
addr = addr/PGSIZE*PGSIZE;
|
||||
|
||||
if (user_llpt[addr/PGSIZE]) {
|
||||
if (!(user_llpt[addr/PGSIZE] & PTE_A)) {
|
||||
user_llpt[addr/PGSIZE] |= PTE_A;
|
||||
} else {
|
||||
assert(!(user_llpt[addr/PGSIZE] & PTE_D) && cause == CAUSE_STORE_PAGE_FAULT);
|
||||
user_llpt[addr/PGSIZE] |= PTE_D;
|
||||
}
|
||||
flush_page(addr);
|
||||
return;
|
||||
}
|
||||
|
||||
freelist_t* node = freelist_head;
|
||||
assert(node);
|
||||
freelist_head = node->next;
|
||||
if (freelist_head == freelist_tail)
|
||||
freelist_tail = 0;
|
||||
|
||||
uintptr_t new_pte = (node->addr >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V | PTE_U | PTE_R | PTE_W | PTE_X;
|
||||
|
||||
if (pf_filter(addr, &filter_encodings, ©_page)) {
|
||||
new_pte = (node->addr >> PGSHIFT << PTE_PPN_SHIFT) | filter_encodings;
|
||||
}
|
||||
|
||||
user_llpt[addr/PGSIZE] = new_pte | PTE_A | PTE_D;
|
||||
flush_page(addr);
|
||||
|
||||
assert(user_mapping[addr/PGSIZE].addr == 0);
|
||||
user_mapping[addr/PGSIZE] = *node;
|
||||
|
||||
uintptr_t sstatus = set_csr(sstatus, SSTATUS_SUM);
|
||||
memcpy((void*)addr, uva2kva(addr), PGSIZE);
|
||||
write_csr(sstatus, sstatus);
|
||||
|
||||
user_llpt[addr/PGSIZE] = new_pte;
|
||||
flush_page(addr);
|
||||
|
||||
asm volatile ("fence.i");
|
||||
}
|
||||
|
||||
void handle_trap(trapframe_t* tf)
|
||||
{
|
||||
if (trap_filter(tf)) {
|
||||
pop_tf(tf);
|
||||
}
|
||||
|
||||
if (tf->cause == CAUSE_USER_ECALL)
|
||||
{
|
||||
int n = tf->gpr[10];
|
||||
|
||||
for (long i = 1; i < MAX_TEST_PAGES; i++)
|
||||
evict(i*PGSIZE);
|
||||
|
||||
terminate(n);
|
||||
}
|
||||
else if (tf->cause == CAUSE_ILLEGAL_INSTRUCTION)
|
||||
{
|
||||
assert(tf->epc % 4 == 0);
|
||||
|
||||
int* fssr;
|
||||
asm ("jal %0, 1f; fssr x0; 1:" : "=r"(fssr));
|
||||
|
||||
if (*(int*)tf->epc == *fssr)
|
||||
terminate(1); // FP test on non-FP hardware. "succeed."
|
||||
else
|
||||
assert(!"illegal instruction");
|
||||
tf->epc += 4;
|
||||
}
|
||||
else if (tf->cause == CAUSE_FETCH_PAGE_FAULT || tf->cause == CAUSE_LOAD_PAGE_FAULT || tf->cause == CAUSE_STORE_PAGE_FAULT)
|
||||
handle_fault(tf->badvaddr, tf->cause);
|
||||
else
|
||||
assert(!"unexpected exception");
|
||||
|
||||
pop_tf(tf);
|
||||
}
|
||||
|
||||
static void coherence_torture()
|
||||
{
|
||||
// cause coherence misses without affecting program semantics
|
||||
uint64_t random = ENTROPY;
|
||||
while (1) {
|
||||
uintptr_t paddr = DRAM_BASE + ((random % (2 * (MAX_TEST_PAGES + 1) * PGSIZE)) & -4);
|
||||
#ifdef __riscv_atomic
|
||||
if (random & 1) // perform a no-op write
|
||||
asm volatile ("amoadd.w zero, zero, (%0)" :: "r"(paddr));
|
||||
else // perform a read
|
||||
#endif
|
||||
asm volatile ("lw zero, (%0)" :: "r"(paddr));
|
||||
random = lfsr63(random);
|
||||
}
|
||||
}
|
||||
|
||||
void vm_boot(uintptr_t test_addr)
|
||||
{
|
||||
uint64_t random = ENTROPY;
|
||||
if (read_csr(mhartid) > 0)
|
||||
coherence_torture();
|
||||
|
||||
_Static_assert(SIZEOF_TRAPFRAME_T == sizeof(trapframe_t), "???");
|
||||
|
||||
#if (MAX_TEST_PAGES > PTES_PER_PT) || (DRAM_BASE % MEGAPAGE_SIZE) != 0
|
||||
# error
|
||||
#endif
|
||||
// map user to lowermost megapage
|
||||
l1pt[0] = ((pte_t)user_l2pt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V;
|
||||
// map kernel to uppermost megapage
|
||||
#if SATP_MODE_CHOICE == SATP_MODE_SV48
|
||||
l1pt[PTES_PER_PT-1] = ((pte_t)kernel_l2pt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V;
|
||||
kernel_l2pt[PTES_PER_PT-1] = ((pte_t)kernel_l3pt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V;
|
||||
kernel_l3pt[PTES_PER_PT-1] = (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_R | PTE_W | PTE_X | PTE_A | PTE_D;
|
||||
user_l2pt[0] = ((pte_t)user_l3pt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V;
|
||||
user_l3pt[0] = ((pte_t)user_llpt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V;
|
||||
#elif SATP_MODE_CHOICE == SATP_MODE_SV39
|
||||
l1pt[PTES_PER_PT-1] = ((pte_t)kernel_l2pt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V;
|
||||
kernel_l2pt[PTES_PER_PT-1] = (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_R | PTE_W | PTE_X | PTE_A | PTE_D;
|
||||
user_l2pt[0] = ((pte_t)user_llpt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V;
|
||||
#elif SATP_MODE_CHOICE == SATP_MODE_SV32
|
||||
l1pt[PTES_PER_PT-1] = (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_R | PTE_W | PTE_X | PTE_A | PTE_D;
|
||||
#else
|
||||
# error
|
||||
#endif
|
||||
uintptr_t vm_choice = SATP_MODE_CHOICE;
|
||||
uintptr_t satp_value = ((uintptr_t)l1pt >> PGSHIFT)
|
||||
| (vm_choice * (SATP_MODE & ~(SATP_MODE<<1)));
|
||||
write_csr(satp, satp_value);
|
||||
if (read_csr(satp) != satp_value)
|
||||
assert(!"unsupported satp mode");
|
||||
flush_page(DRAM_BASE);
|
||||
|
||||
// Set up PMPs if present, ignoring illegal instruction trap if not.
|
||||
uintptr_t pmpc = PMP_NAPOT | PMP_R | PMP_W | PMP_X;
|
||||
uintptr_t pmpa = ((uintptr_t)1 << (__riscv_xlen == 32 ? 31 : 53)) - 1;
|
||||
asm volatile ("la t0, 1f\n\t"
|
||||
"csrrw t0, mtvec, t0\n\t"
|
||||
"csrw pmpaddr0, %1\n\t"
|
||||
"csrw pmpcfg0, %0\n\t"
|
||||
".align 2\n\t"
|
||||
"1: csrw mtvec, t0"
|
||||
: : "r" (pmpc), "r" (pmpa) : "t0");
|
||||
|
||||
// set up supervisor trap handling
|
||||
write_csr(stvec, pa2kva(trap_entry));
|
||||
write_csr(sscratch, pa2kva(read_csr(mscratch)));
|
||||
write_csr(medeleg,
|
||||
(1 << CAUSE_USER_ECALL) |
|
||||
(1 << CAUSE_FETCH_PAGE_FAULT) |
|
||||
(1 << CAUSE_LOAD_PAGE_FAULT) |
|
||||
(1 << CAUSE_STORE_PAGE_FAULT));
|
||||
// FPU on; accelerator on; vector unit on
|
||||
write_csr(mstatus, MSTATUS_FS | MSTATUS_XS | MSTATUS_VS);
|
||||
write_csr(mie, 0);
|
||||
|
||||
random = 1 + (random % MAX_TEST_PAGES);
|
||||
freelist_head = pa2kva((void*)&freelist_nodes[0]);
|
||||
freelist_tail = pa2kva(&freelist_nodes[MAX_TEST_PAGES-1]);
|
||||
for (long i = 0; i < MAX_TEST_PAGES; i++)
|
||||
{
|
||||
freelist_nodes[i].addr = DRAM_BASE + (MAX_TEST_PAGES + random)*PGSIZE;
|
||||
freelist_nodes[i].next = pa2kva(&freelist_nodes[i+1]);
|
||||
random = LFSR_NEXT(random);
|
||||
}
|
||||
freelist_nodes[MAX_TEST_PAGES-1].next = 0;
|
||||
|
||||
trapframe_t tf;
|
||||
memset(&tf, 0, sizeof(tf));
|
||||
tf.epc = test_addr - DRAM_BASE;
|
||||
pop_tf(&tf);
|
||||
}
|
||||
@@ -3,6 +3,7 @@
|
||||
# scp Cprograms/main.c home:/home/akilan/cheri/output/sdk/bin/
|
||||
|
||||
scp cheri.S home:/home/akilan/cheri/output/sdk/bin/
|
||||
# scp cheriTest.S home:/home/akilan/cheri/output/sdk/bin/
|
||||
|
||||
# Run compiled instruction remotely
|
||||
ssh home 'cd /home/akilan/cheri/output/sdk/bin/ && ./clang --target=riscv64-unknown-elf -march=rv64gcxcheri -mabi=l64pc128 -nostdlib -nostartfiles -Wl,-Ttext=0x80000000 -o testC cheri.S'
|
||||
|
||||
@@ -1,56 +1,126 @@
|
||||
.section .text
|
||||
.section .data
|
||||
.align 12 # All tables must be 4KB aligned
|
||||
|
||||
# --- Level 2: Root Table (At 0x80001000) ---
|
||||
l2_table:
|
||||
.quad 0
|
||||
.quad 0
|
||||
# Points to l1_table (0x80002000).
|
||||
# PPN is 0x80002. Shifted left by 10 = 0x20000800. Flag V=1.
|
||||
.quad (0x80002 << 10) | 0x1
|
||||
.fill 509, 8, 0
|
||||
|
||||
# --- Level 1: Middle Table (At 0x80002000) ---
|
||||
l1_table:
|
||||
# Points to l0_table (0x80003000).
|
||||
# PPN is 0x80003. Shifted left by 10 = 0x20000C00. Flag V=1.
|
||||
.quad (0x80003 << 10) | 0x1
|
||||
.fill 511, 8, 0
|
||||
|
||||
# --- Level 0: Leaf Table (At 0x80003000) ---
|
||||
l0_table:
|
||||
# Maps the actual code/data at 0x80000000.
|
||||
# PPN is 0x80000. Flags: D A G U R W X V (0xCF)
|
||||
.quad (0x80000 << 10) | 0xCF
|
||||
.fill 511, 8, 0
|
||||
|
||||
.section .text
|
||||
.globl _start
|
||||
.align 4
|
||||
_start:
|
||||
# 1. Setup the Page Table Root (Sv39)
|
||||
# The PPN points to the physical location of your root table.
|
||||
li t0, (0x80000000 >> 12)
|
||||
li t1, (8 << 60) # Mode 8 = Sv39
|
||||
# 1. Setup satp to point to the L2 (Root) table
|
||||
cllc ca0, l2_table
|
||||
cgetaddr t0, ca0
|
||||
srli t0, t0, 12 # PPN of the root
|
||||
li t1, (8 << 60) # Sv39 mode
|
||||
or t0, t0, t1
|
||||
csrw satp, t0
|
||||
sfence.vma # All addresses below are now VIRTUAL
|
||||
csrw satp, t0 # ENABLE PAGING
|
||||
|
||||
# ---------------------------------------------------------------
|
||||
|
||||
# 2. Get the root capability (PCC)
|
||||
# Since we are running in VA space, ct0 now describes a VA range.
|
||||
cspecialr ct0, pcc
|
||||
|
||||
# Use csetaddr to build a stack capability
|
||||
li t0, 0x80002100 # fixed top-of-stack address
|
||||
csetaddr csp, ct0, t0
|
||||
|
||||
# bound it to 8 bytes (size of dword)
|
||||
li t2, 8
|
||||
csetbounds csp, csp, t2
|
||||
# li t5, 4
|
||||
# cincoffsetimm csp, csp, 10
|
||||
|
||||
# Read bounds
|
||||
# cgetbase t3, csp
|
||||
ld t0, 0(csp)
|
||||
|
||||
# ----------------------------------------------------------------
|
||||
# 3. Create Virtual Address Silos (ca1 - ca4)
|
||||
# ----------------------------------------------------------------
|
||||
|
||||
# Silo 1: VA 0x80006000
|
||||
li t1, 0x80006000
|
||||
|
||||
# Use csetaddr to build a stack capability
|
||||
li t1, 0x80006000 # fixed top-of-stack address
|
||||
csetaddr ca1, ct0, t1
|
||||
li t2, 8
|
||||
csetbounds ca1, ca1, t2
|
||||
ld t0, 0(ca1) # Accessing VA 0x80006000
|
||||
|
||||
# ... (Repeat for ca2, ca3, ca4 as in your previous logic) ...
|
||||
# bound it to 8 bytes (size of dword)
|
||||
li t1, 8
|
||||
csetbounds ca1, ca1, t1
|
||||
# cincoffsetimm ca1, ca1, 8
|
||||
|
||||
# Read bounds
|
||||
# cgetbase t3, csp
|
||||
ld t0, 0(ca1)
|
||||
|
||||
# ----------------------------------------------------------------
|
||||
# 4. FIX: The 'tohost' Exit Mechanism (Virtual Address)
|
||||
|
||||
# Use csetaddr to build a stack capability
|
||||
li t1, 0x80008000 # fixed top-of-stack address
|
||||
csetaddr ca2, ct0, t1
|
||||
|
||||
# bound it to 8 bytes (size of dword)
|
||||
li t1, 8
|
||||
csetbounds ca2, ca2, t1
|
||||
# cincoffsetimm ca2, ca2, 6
|
||||
|
||||
# Read bounds
|
||||
# cgetbase t3, csp
|
||||
ld t0, 0(ca2)
|
||||
|
||||
# ----------------------------------------------------------------
|
||||
|
||||
# 'la' loads the Virtual Address of the label 'tohost'
|
||||
la t0, tohost
|
||||
|
||||
# We MUST derive c1 from a valid capability (ct0) to keep the TAG bit
|
||||
csetaddr c1, ct0, t0
|
||||
|
||||
# Set bounds to 8 bytes (size of a dword)
|
||||
li t1, 8
|
||||
csetbounds c1, c1, t1
|
||||
# Use csetaddr to build a stack capability
|
||||
li t1, 0x80009000 # fixed top-of-stack address
|
||||
csetaddr ca3, ct0, t1
|
||||
|
||||
# Final Store to signal the simulator (Success = 1)
|
||||
# bound it to 8 bytes (size of dword)
|
||||
li t1, 8
|
||||
csetbounds ca3, ca3, t1
|
||||
# cincoffsetimm ca3, ca3, 6
|
||||
|
||||
# Read bounds
|
||||
# cgetbase t3, csp
|
||||
ld t0, 0(ca3)
|
||||
|
||||
# ----------------------------------------------------------------
|
||||
# Use csetaddr to build a stack capability
|
||||
li t1, 0x80002000 # fixed top-of-stack address
|
||||
csetaddr ca4, ct0, t1
|
||||
|
||||
# bound it to 8 bytes (size of dword)
|
||||
li t1, 8
|
||||
csetbounds ca4, ca4, t1
|
||||
# cincoffsetimm ca4, ca4, 1
|
||||
|
||||
# Read bounds
|
||||
# cgetbase t3, csp
|
||||
ld t0, 0(ca4)
|
||||
|
||||
# ----------------------------------------------------------------
|
||||
|
||||
|
||||
# derive capability from PCC
|
||||
# csetaddr c1, ct0, t0
|
||||
|
||||
# la t0, tohost
|
||||
li t1, 1
|
||||
csd t1, 0(c1) # Store 1 to the VA of tohost
|
||||
csd t1, 0(c1)
|
||||
|
||||
|
||||
# ----------------------------------------------------------------
|
||||
# Data Section: Needs to be mapped in your Sv39 Page Tables
|
||||
# ----------------------------------------------------------------
|
||||
.section ".tohost","aw",@progbits
|
||||
.align 6
|
||||
.globl tohost
|
||||
tohost: .dword 0
|
||||
.globl fromhost
|
||||
fromhost: .dword 0
|
||||
49
Tests/isa/cheriTest.S
Normal file
49
Tests/isa/cheriTest.S
Normal file
@@ -0,0 +1,49 @@
|
||||
.section .data
|
||||
.align 12
|
||||
# Root Table (L2)
|
||||
# Since we map 1GiB, this is the ONLY table we need.
|
||||
l2_table:
|
||||
.quad 0
|
||||
.quad 0
|
||||
# Entry 2 maps 0x80000000 - 0xBFFFFFFF
|
||||
# PPN 0x80000, Flags: D A G U R W X V (0xCF)
|
||||
.quad (0x80000 << 10) | 0xCF
|
||||
.fill 509, 8, 0
|
||||
|
||||
.section .text
|
||||
.globl _start
|
||||
.align 4
|
||||
_start:
|
||||
# 1. Get the address of our table
|
||||
cllc ca0, l2_table
|
||||
cgetaddr t0, ca0
|
||||
|
||||
# 2. Convert address to PPN
|
||||
srli t0, t0, 12
|
||||
|
||||
# 3. Construct SATP with Mode 8 (Sv39)
|
||||
# The FIXME suggests bit 63 must be 1.
|
||||
li t1, 8
|
||||
slli t1, t1, 60
|
||||
or t0, t0, t1 # t0 = (8 << 60) | PPN
|
||||
|
||||
# 4. Critical Write Sequence
|
||||
sfence.vma # Flush before enabling
|
||||
csrw sptbr, t0 # Write to SATP
|
||||
sfence.vma # Flush after enabling
|
||||
|
||||
# 5. Transition to Virtual Space
|
||||
# We load an address from the .data section (0x80002000)
|
||||
# If paging is ON, the DTLB trace should now show (sv39)
|
||||
li t1, 0x80002000
|
||||
cspecialr ca1, pcc
|
||||
csetaddr ca1, ca1, t1
|
||||
|
||||
ld t2, 0(ca1) # Trigger a DTLB lookup
|
||||
|
||||
# 6. Exit / Finish
|
||||
# (Assuming your tohost logic)
|
||||
li t1, 1
|
||||
csd t1, 0(c1)
|
||||
|
||||
loop: j loop
|
||||
BIN
Tests/isa/testC
BIN
Tests/isa/testC
Binary file not shown.
@@ -4,7 +4,8 @@ make[1]: 'elf_to_hex' is up to date.
|
||||
make[1]: Leaving directory '/Users/akilan/Documents/Cheri/Test/Reverse/Test/Toooba/Tests/elf_to_hex'
|
||||
../../Tests/elf_to_hex/elf_to_hex ../../Tests/isa/testC Mem.hex
|
||||
c_mem_load_elf: ../../Tests/isa/testC is a 64-bit ELF file
|
||||
Section .text : addr 80000000 to addr 80000084; size 0x 84 (= 132) bytes
|
||||
Section .text : addr 80000000 to addr 8000008c; size 0x 8c (= 140) bytes
|
||||
Section .data : addr 80002000 to addr 80005000; size 0x 3000 (= 12288) bytes
|
||||
Section .riscv.attributes: Ignored
|
||||
Section .comment : Ignored
|
||||
Section .symtab : Searching for addresses of '_start', 'exit' and 'tohost' symbols
|
||||
@@ -14,11 +15,11 @@ Writing symbols to: symbol_table.txt
|
||||
Section .shstrtab : Ignored
|
||||
Section .strtab : Ignored
|
||||
Min addr: 80000000 (hex)
|
||||
Max addr: 80000083 (hex)
|
||||
Max addr: 80004fff (hex)
|
||||
Writing mem hex to file 'Mem.hex'
|
||||
Subtracting 0x80000000 base from addresses
|
||||
./exe_HW_sim +v1 +tohost
|
||||
Warning: file 'Mem.hex' for memory 'rf' has a gap at addresses 5 to 33554430.
|
||||
Warning: file 'Mem.hex' for memory 'rf' has a gap at addresses 640 to 33554430.
|
||||
1: top.soc_top.rl_reset_start_initial ...
|
||||
calling cycle
|
||||
calling cycle
|
||||
@@ -271,6 +272,7 @@ calling cycle
|
||||
calling cycle
|
||||
instret:2 PC:0x1ffff0000000000000000000000001008 instr:0xf1402573 iType:Csr [doCommitSystemInst] 224
|
||||
calling cycle
|
||||
225: top.soc_top.corew_proc.core_0.rule prepareCachesAndTlbs: updating VMInfo
|
||||
calling cycle
|
||||
calling cycle
|
||||
calling cycle
|
||||
@@ -1210,34 +1212,47 @@ calling cycle
|
||||
calling cycle
|
||||
calling cycle
|
||||
calling cycle
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffff }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00080000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h0a, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00002000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
calling cycle
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Or, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h06}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h47, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h48, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h06, rn2 'h06}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003f }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Srl, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h48, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h46, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } }
|
||||
calling cycle
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h06, rn2 'h06}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003f }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffff }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
calling cycle
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Or, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h06}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h48, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
|
||||
calling cycle
|
||||
[RFile] wr_ 0: r 46 <= 3fffffffffffffffcfff00001fffff44000000
|
||||
[RFile] wr_ 1: r 45 <= 0000000000020000000000001fffff44000000
|
||||
[RFile] wr_ 1: r 45 <= 0000000020000800000000001fffff44000000
|
||||
calling cycle
|
||||
[RFile] wr_ 1: r 47 <= 2000000000000000080000001fffff44000000
|
||||
instret:5 PC:0x1ffff0000000000000000000080000000 instr:0x000802b7 iType:Alu [doCommitNormalInst [0]] 1155
|
||||
instret:6 PC:0x1ffff0000000000000000000080000004 instr:0x0000537d iType:Alu [doCommitNormalInst [1]] 1155
|
||||
[RFile] wr_ 0: r 46 <= 0000000020000800000000001fffff44000000
|
||||
instret:5 PC:0x1ffff0000000000000000000080000000 instr:0x00002517 iType:Auipc [doCommitNormalInst [0]] 1155
|
||||
calling cycle
|
||||
[RFile] wr_ 0: r 48 <= 2000000000020000080000001fffff44000000
|
||||
instret:7 PC:0x1ffff0000000000000000000080000006 instr:0x0000137e iType:Alu [doCommitNormalInst [0]] 1156
|
||||
[RFile] wr_ 1: r 47 <= 0000000020000800000000001fffff44000000
|
||||
instret:6 PC:0x1ffff0000000000000000000080000004 instr:0x0005155b iType:Cap [doCommitNormalInst [0]] 1156
|
||||
calling cycle
|
||||
instret:8 PC:0x1ffff0000000000000000000080000008 instr:0x0062e2b3 iType:Alu [doCommitNormalInst [0]] 1157
|
||||
[RFile] wr_ 0: r 48 <= 0000000000020000800000001fffff44000000
|
||||
[RFile] wr_ 1: r 49 <= 3fffffffffffffffcfff00001fffff44000000
|
||||
instret:7 PC:0x1ffff0000000000000000000080000008 instr:0x000082aa iType:Alu [doCommitNormalInst [0]] 1157
|
||||
calling cycle
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Csr, execFunc: tagged Alu Csrw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Valid csrAddrSATP, scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Valid 'h48, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
[RFile] wr_ 0: r 4a <= 2000000000000000080000001fffff44000000
|
||||
instret:8 PC:0x1ffff000000000000000000008000000a instr:0x00c2d293 iType:Alu [doCommitNormalInst [0]] 1158
|
||||
instret:9 PC:0x1ffff000000000000000000008000000e instr:0x0000537d iType:Alu [doCommitNormalInst [1]] 1158
|
||||
calling cycle
|
||||
[RFile] wr_ 1: r 4b <= 2000000000020000880000001fffff44000000
|
||||
instret:10 PC:0x1ffff0000000000000000000080000010 instr:0x0000137e iType:Alu [doCommitNormalInst [0]] 1159
|
||||
calling cycle
|
||||
instret:11 PC:0x1ffff0000000000000000000080000012 instr:0x0062e2b3 iType:Alu [doCommitNormalInst [0]] 1160
|
||||
calling cycle
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Csr, execFunc: tagged Alu Csrw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Valid csrAddrSATP, scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
calling cycle
|
||||
calling cycle
|
||||
calling cycle
|
||||
calling cycle
|
||||
calling cycle
|
||||
instret:9 PC:0x1ffff000000000000000000008000000c instr:0x18029073 iType:Csr [doCommitSystemInst] 1163
|
||||
instret:12 PC:0x1ffff0000000000000000000080000016 instr:0x18029073 iType:Csr [doCommitSystemInst] 1166
|
||||
calling cycle
|
||||
1167: top.soc_top.corew_proc.core_0.rule prepareCachesAndTlbs: updating VMInfo
|
||||
calling cycle
|
||||
[DTLB] flush begin
|
||||
calling cycle
|
||||
@@ -1509,28 +1524,95 @@ calling cycle
|
||||
calling cycle
|
||||
calling cycle
|
||||
calling cycle
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h40001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipcc, execFunc: tagged Alu Add, capFunc: tagged CapModify tagged SpecialRW tagged TCC , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Valid scrAddrPCC, imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
calling cycle
|
||||
instret:10 PC:0x1ffff0000000000000000000080000010 instr:0x12000073 iType:SFence [doCommitSystemInst] 1434
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000100 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
calling cycle
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetAddr Src1Addr, capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
|
||||
calling cycle
|
||||
[DTLB] flush begin
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds SetBoundsRounding, capChecks: CapChecks {rn1 'h02, rn2 'h07}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
|
||||
calling cycle
|
||||
[RFile] wr_ 0: r 4e <= 0000000010000400000000001fffff44000000
|
||||
[RFile] wr_ 1: r 4d <= 40000000200000068000ffff1fffff44000000
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h06, rn2 'h06}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h40003000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
calling cycle
|
||||
[RFile] wr_ 1: r 4f <= 0000000020000800000000001fffff44000000
|
||||
instret:13 PC:0x1ffff000000000000000000008000001a instr:0x020002db iType:Auipcc [doCommitNormalInst [0]] 1441
|
||||
instret:14 PC:0x1ffff000000000000000000008000001e instr:0x400012b7 iType:Alu [doCommitNormalInst [1]] 1441
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetAddr Src1Addr, capChecks: CapChecks {rn1 'h06, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h54, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
calling cycle
|
||||
[RFile] wr_ 0: r 50 <= 0000000020000840000000001fffff44000000
|
||||
14420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
instret:15 PC:0x1ffff0000000000000000000080000022 instr:0x00000286 iType:Alu [doCommitNormalInst [0]] 1442
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds SetBoundsRounding, capChecks: CapChecks {rn1 'h0b, rn2 'h06}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
|
||||
calling cycle
|
||||
[RFile] wr_ 0: r 52 <= 0000000000000002000000001fffff44000000
|
||||
[RFile] wr_ 1: r 51 <= 0000000020000840000000001fffff44000000
|
||||
14430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
|
||||
instret:16 PC:0x1ffff0000000000000000000080000024 instr:0x10028293 iType:Alu [doCommitNormalInst [0]] 1443
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h06, rn2 'h06}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h10001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
calling cycle
|
||||
[RFile] wr_ 1: r 53 <= 0000000020000840210000001ffff808422100
|
||||
14440 : [doExeMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080002100 o: 'h0000000080002100 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002100 o: 'h0000000080002100 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V True True True True True True True True False False False False False False False False > }, spec_bits: 'h000 }
|
||||
DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002100, write: False, capStore: False, potentialCapLoad: False }
|
||||
instret:17 PC:0x1ffff0000000000000000000080000028 instr:0x2052815b iType:Cap [doCommitNormalInst [0]] 1444
|
||||
instret:18 PC:0x1ffff000000000000000000008000002c instr:0x000043a1 iType:Alu [doCommitNormalInst [1]] 1444
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetAddr Src1Addr, capChecks: CapChecks {rn1 'h06, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
|
||||
calling cycle
|
||||
[RFile] wr_ 1: r 55 <= 0000000010000c00000000001fffff44000000
|
||||
14450 : [doFinishMem] DTlbResp { resp: <'h0000000080002100,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, vaddr: v: True a: 'h0000000080002100 o: 'h0000000080002100 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002100, check_high: 'h00000000080002108, check_inclusive: True } }, specBits: 'h000 }
|
||||
14450 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080002100, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, pcHash: 'h8032 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
|
||||
14450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080002100, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8032 }
|
||||
instret:19 PC:0x1ffff000000000000000000008000002e instr:0x1071015b iType:Cap [doCommitNormalInst [0]] 1445
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds SetBoundsRounding, capChecks: CapChecks {rn1 'h0c, rn2 'h06}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0c, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
|
||||
calling cycle
|
||||
[RFile] wr_ 0: r 56 <= 0000000020001800000000001fffff44000000
|
||||
[RFile] wr_ 1: r 58 <= 0000000000000002000000001fffff44000000
|
||||
14460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False True False True >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > > } }, repInfo: , setAuxData: tagged Invalid }
|
||||
14460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080002100, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8032 }
|
||||
14460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h06, rn2 'h06}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000009 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00080000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
calling cycle
|
||||
[RFile] wr_ 1: r 5b <= 0000000004000400000000001fffff44000000
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetAddr Src1Addr, capChecks: CapChecks {rn1 'h06, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h06, rn2 'h06}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
|
||||
calling cycle
|
||||
14480 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080002100, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8032 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002100, fromState: I, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False }
|
||||
[RFile] wr_ 0: r 5c <= 0000000020002000000000001fffff44000000
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds SetBoundsRounding, capChecks: CapChecks {rn1 'h0d, rn2 'h06}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
calling cycle
|
||||
[RFile] wr_ 0: r 5e <= 0000000000000002000000001fffff44000000
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h40001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
|
||||
calling cycle
|
||||
[RFile] wr_ 1: r 61 <= 0000000000020000000000001fffff44000000
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetAddr Src1Addr, capChecks: CapChecks {rn1 'h06, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Valid 'h67, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h06, rn2 'h06}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
|
||||
calling cycle
|
||||
[RFile] wr_ 0: r 62 <= 0000000000020002400000001fffff44000000
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
calling cycle
|
||||
[RFile] wr_ 1: r 63 <= 0000000020002400000000001fffff44000000
|
||||
calling cycle
|
||||
[RFile] wr_ 1: r 65 <= 0000000000000002000000001fffff44000000
|
||||
calling cycle
|
||||
[RFile] wr_ 1: r 68 <= 0000000010000400000000001fffff44000000
|
||||
calling cycle
|
||||
[RFile] wr_ 1: r 69 <= 0000000020000800000000001fffff44000000
|
||||
calling cycle
|
||||
[RFile] wr_ 1: r 6b <= 0000000000000002000000001fffff44000000
|
||||
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|
||||
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|
||||
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|
||||
@@ -1571,389 +1653,44 @@ calling cycle
|
||||
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|
||||
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|
||||
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|
||||
14960 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002100, toState: E, child: , data: tagged Valid CLine { tag: <V False False False False >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > }, id: 'h0 }
|
||||
calling cycle
|
||||
14970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: <V False False False False >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } }, repInfo: , setAuxData: tagged Invalid }
|
||||
14970 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs:
|
||||
14970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080002100, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8032 }
|
||||
14970 : [Ld resp] 'h01; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }
|
||||
14970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False False False False >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } ; tagged Invalid
|
||||
calling cycle
|
||||
14980 : [doRespLdMem] 'h01; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > } }
|
||||
[RFile] wr_ 3: r 54 <= 0000000000000000000000001fffff44000000
|
||||
calling cycle
|
||||
[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False }, paddr: 'h0000000080002100, isMMIO: False, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, fault: tagged Invalid , allowCap: False, killed: tagged Invalid }
|
||||
calling cycle
|
||||
15000 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
instret:20 PC:0x1ffff0000000000000000000080000032 instr:0x00006282 iType:Ld [doCommitNormalInst [0]] 1500
|
||||
instret:21 PC:0x1ffff0000000000000000000080000034 instr:0x40003337 iType:Alu [doCommitNormalInst [1]] 1500
|
||||
calling cycle
|
||||
[RFile] wr_ 0: r 57 <= 0000000020001800000000001fffff44000000
|
||||
15010 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
|
||||
instret:22 PC:0x1ffff0000000000000000000080000038 instr:0x00000306 iType:Alu [doCommitNormalInst [0]] 1501
|
||||
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||||
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|
||||
[DTLB] flush done
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00080000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipcc, execFunc: tagged Alu Add, capFunc: tagged CapModify tagged SpecialRW tagged TCC , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Valid scrAddrPCC, imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
calling cycle
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
calling cycle
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetAddr Src1Addr, capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h4e, src2: tagged Valid 'h4e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
|
||||
calling cycle
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds SetBoundsRounding, capChecks: CapChecks {rn1 'h02, rn2 'h07}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Valid 'h50, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
|
||||
calling cycle
|
||||
[RFile] wr_ 0: r 4c <= 0000000000020000000000001fffff44000000
|
||||
[RFile] wr_ 1: r 4b <= 40000000200000050000ffff1fffff44000000
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h06, rn2 'h06}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h53, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h40003000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
calling cycle
|
||||
[RFile] wr_ 1: r 4d <= 0000000000020000400000001fffff44000000
|
||||
instret:11 PC:0x1ffff0000000000000000000080000014 instr:0x020002db iType:Auipcc [doCommitNormalInst [0]] 1709
|
||||
instret:12 PC:0x1ffff0000000000000000000080000018 instr:0x000802b7 iType:Alu [doCommitNormalInst [1]] 1709
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetAddr Src1Addr, capChecks: CapChecks {rn1 'h06, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Valid 'h52, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
calling cycle
|
||||
[RFile] wr_ 0: r 4e <= 0000000020000400000000001fffff44000000
|
||||
17100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
instret:13 PC:0x1ffff000000000000000000008000001c instr:0x00002285 iType:Alu [doCommitNormalInst [0]] 1710
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds SetBoundsRounding, capChecks: CapChecks {rn1 'h0b, rn2 'h06}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h56, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
|
||||
calling cycle
|
||||
[RFile] wr_ 0: r 50 <= 0000000000000002000000001fffff44000000
|
||||
[RFile] wr_ 1: r 4f <= 0000000020000400000000001fffff44000000
|
||||
17110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
|
||||
instret:14 PC:0x1ffff000000000000000000008000001e instr:0x000002b2 iType:Alu [doCommitNormalInst [0]] 1711
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h06, rn2 'h06}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000003 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h10001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
calling cycle
|
||||
[RFile] wr_ 1: r 51 <= 0000000020000400100000001ffff804021000
|
||||
17120 : [doExeMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V True True True True True True True True False False False False False False False False > }, spec_bits: 'h000 }
|
||||
DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001000, write: False, capStore: False, potentialCapLoad: False }
|
||||
instret:15 PC:0x1ffff0000000000000000000080000020 instr:0x2052815b iType:Cap [doCommitNormalInst [0]] 1712
|
||||
instret:16 PC:0x1ffff0000000000000000000080000024 instr:0x000043a1 iType:Alu [doCommitNormalInst [1]] 1712
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetAddr Src1Addr, capChecks: CapChecks {rn1 'h06, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h5a, src2: tagged Valid 'h58, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
|
||||
calling cycle
|
||||
[RFile] wr_ 1: r 53 <= 0000000010000c00000000001fffff44000000
|
||||
17130 : [doFinishMem] DTlbResp { resp: <'h0000000080001000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, vaddr: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001000, check_high: 'h00000000080001008, check_inclusive: True } }, specBits: 'h000 }
|
||||
17130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080001000, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, pcHash: 'h802a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
|
||||
17130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080001000, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802a }
|
||||
instret:17 PC:0x1ffff0000000000000000000080000026 instr:0x1071015b iType:Cap [doCommitNormalInst [0]] 1713
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds SetBoundsRounding, capChecks: CapChecks {rn1 'h0c, rn2 'h06}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Valid 'h5c, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0c, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
|
||||
calling cycle
|
||||
[RFile] wr_ 0: r 54 <= 0000000020001800000000001fffff44000000
|
||||
[RFile] wr_ 1: r 56 <= 0000000000000002000000001fffff44000000
|
||||
17140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False True False True >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > > } }, repInfo: , setAuxData: tagged Invalid }
|
||||
17140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080001000, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802a }
|
||||
17140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h06, rn2 'h06}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000009 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00080000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
calling cycle
|
||||
[RFile] wr_ 1: r 59 <= 0000000004000400000000001fffff44000000
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetAddr Src1Addr, capChecks: CapChecks {rn1 'h06, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Valid 'h5e, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h62, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h06, rn2 'h06}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h60, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
|
||||
calling cycle
|
||||
17160 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080001000, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802a } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080001000, fromState: I, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False }
|
||||
[RFile] wr_ 0: r 5a <= 0000000020002000000000001fffff44000000
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds SetBoundsRounding, capChecks: CapChecks {rn1 'h0d, rn2 'h06}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h62, src2: tagged Valid 'h63, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
calling cycle
|
||||
[RFile] wr_ 0: r 5c <= 0000000000000002000000001fffff44000000
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h40001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
|
||||
calling cycle
|
||||
[RFile] wr_ 1: r 5f <= 0000000000020000000000001fffff44000000
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetAddr Src1Addr, capChecks: CapChecks {rn1 'h06, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h06, rn2 'h06}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
|
||||
calling cycle
|
||||
[RFile] wr_ 0: r 60 <= 0000000000020002400000001fffff44000000
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds SetBoundsRounding, capChecks: CapChecks {rn1 'h0e, rn2 'h06}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Valid 'h69, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
calling cycle
|
||||
[RFile] wr_ 1: r 61 <= 0000000020002400000000001fffff44000000
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0e, rn2 'h0e, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
|
||||
calling cycle
|
||||
[RFile] wr_ 1: r 63 <= 0000000000000002000000001fffff44000000
|
||||
calling cycle
|
||||
[RFile] wr_ 1: r 66 <= 0000000010000400000000001fffff44000000
|
||||
calling cycle
|
||||
[RFile] wr_ 1: r 67 <= 0000000020000800000000001fffff44000000
|
||||
calling cycle
|
||||
[RFile] wr_ 1: r 69 <= 0000000000000002000000001fffff44000000
|
||||
calling cycle
|
||||
[RFile] wr_ 1: r 6c <= 0000000000000000400000001fffff44000000
|
||||
calling cycle
|
||||
calling cycle
|
||||
calling cycle
|
||||
calling cycle
|
||||
calling cycle
|
||||
calling cycle
|
||||
calling cycle
|
||||
calling cycle
|
||||
calling cycle
|
||||
calling cycle
|
||||
calling cycle
|
||||
calling cycle
|
||||
calling cycle
|
||||
calling cycle
|
||||
calling cycle
|
||||
calling cycle
|
||||
calling cycle
|
||||
calling cycle
|
||||
calling cycle
|
||||
calling cycle
|
||||
calling cycle
|
||||
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|
||||
calling cycle
|
||||
calling cycle
|
||||
calling cycle
|
||||
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|
||||
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|
||||
calling cycle
|
||||
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|
||||
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|
||||
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|
||||
calling cycle
|
||||
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|
||||
calling cycle
|
||||
calling cycle
|
||||
calling cycle
|
||||
calling cycle
|
||||
calling cycle
|
||||
calling cycle
|
||||
17640 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080001000, toState: E, child: , data: tagged Valid CLine { tag: <V False False False False >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > > }, id: 'h0 }
|
||||
calling cycle
|
||||
17650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: <V False False False False >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > > } }, repInfo: , setAuxData: tagged Invalid }
|
||||
17650 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs:
|
||||
17650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080001000, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802a }
|
||||
17650 : [Ld resp] 'h01; TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }
|
||||
17650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False False False False >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > > } ; tagged Invalid
|
||||
calling cycle
|
||||
17660 : [doRespLdMem] 'h01; TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'h0000000000000000 > } }
|
||||
[RFile] wr_ 3: r 52 <= 2aaaaaaaaaaaaaaa8aaa00001fffff44000000
|
||||
calling cycle
|
||||
[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False }, paddr: 'h0000000080001000, isMMIO: False, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, fault: tagged Invalid , allowCap: False, killed: tagged Invalid }
|
||||
calling cycle
|
||||
17680 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
instret:18 PC:0x1ffff000000000000000000008000002a instr:0x00006282 iType:Ld [doCommitNormalInst [0]] 1768
|
||||
instret:19 PC:0x1ffff000000000000000000008000002c instr:0x40003337 iType:Alu [doCommitNormalInst [1]] 1768
|
||||
calling cycle
|
||||
[RFile] wr_ 0: r 55 <= 0000000020001800000000001fffff44000000
|
||||
17690 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h57, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
|
||||
instret:20 PC:0x1ffff0000000000000000000080000030 instr:0x00000306 iType:Alu [doCommitNormalInst [0]] 1769
|
||||
calling cycle
|
||||
[RFile] wr_ 0: r 57 <= 0000000020001800200000001ffff808022000
|
||||
17700 : [doExeMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080006000 o: 'h0000000080006000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080006000 o: 'h0000000080006000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V True True True True True True True True False False False False False False False False > }, spec_bits: 'h000 }
|
||||
[RFile] wr_ 0: r 59 <= 0000000020001800200000001ffff808022000
|
||||
15020 : [doExeMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080006000 o: 'h0000000080006000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080006000 o: 'h0000000080006000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V True True True True True True True True False False False False False False False False > }, spec_bits: 'h000 }
|
||||
DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080006000, write: False, capStore: False, potentialCapLoad: False }
|
||||
instret:21 PC:0x1ffff0000000000000000000080000032 instr:0x206285db iType:Cap [doCommitNormalInst [0]] 1770
|
||||
instret:22 PC:0x1ffff0000000000000000000080000036 instr:0x00004321 iType:Alu [doCommitNormalInst [1]] 1770
|
||||
instret:23 PC:0x1ffff000000000000000000008000003a instr:0x206285db iType:Cap [doCommitNormalInst [0]] 1502
|
||||
instret:24 PC:0x1ffff000000000000000000008000003e instr:0x00004321 iType:Alu [doCommitNormalInst [1]] 1502
|
||||
calling cycle
|
||||
17710 : [doFinishMem] DTlbResp { resp: <'h0000000080006000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, vaddr: v: True a: 'h0000000080006000 o: 'h0000000080006000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080006000, check_high: 'h00000000080006008, check_inclusive: True } }, specBits: 'h000 }
|
||||
17710 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080006000, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, pcHash: 'h803c } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
|
||||
17710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080006000, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h803c }
|
||||
instret:23 PC:0x1ffff0000000000000000000080000038 instr:0x106585db iType:Cap [doCommitNormalInst [0]] 1771
|
||||
15030 : [doFinishMem] DTlbResp { resp: <'h0000000080006000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, vaddr: v: True a: 'h0000000080006000 o: 'h0000000080006000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080006000, check_high: 'h00000000080006008, check_inclusive: True } }, specBits: 'h000 }
|
||||
15030 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080006000, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, pcHash: 'h8044 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
|
||||
15030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080006000, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 }
|
||||
instret:25 PC:0x1ffff0000000000000000000080000040 instr:0x106585db iType:Cap [doCommitNormalInst [0]] 1503
|
||||
calling cycle
|
||||
17720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False True False True >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > > } }, repInfo: , setAuxData: tagged Invalid }
|
||||
17720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080006000, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h803c }
|
||||
17720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace
|
||||
15040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False True False True >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > > } }, repInfo: , setAuxData: tagged Invalid }
|
||||
15040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080006000, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 }
|
||||
15040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace
|
||||
calling cycle
|
||||
calling cycle
|
||||
17740 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080006000, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h803c } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080006000, fromState: I, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False }
|
||||
15060 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080006000, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080006000, fromState: I, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False }
|
||||
calling cycle
|
||||
calling cycle
|
||||
calling cycle
|
||||
@@ -1978,16 +1715,22 @@ calling cycle
|
||||
calling cycle
|
||||
calling cycle
|
||||
calling cycle
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h01, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds SetBoundsRounding, capChecks: CapChecks {rn1 'h0e, rn2 'h06}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0e, rn2 'h0e, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
|
||||
calling cycle
|
||||
17990 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h01, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h01, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } }
|
||||
calling cycle
|
||||
18000 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h01, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
|
||||
calling cycle
|
||||
18010 : [doExeMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h01, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V True True True True True True True True False False False False False False False False > }, spec_bits: 'h000 }
|
||||
15330 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h01, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
calling cycle
|
||||
15340 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h01, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
|
||||
calling cycle
|
||||
[RFile] wr_ 1: r 6e <= 0000000000000000400000001fffff44000000
|
||||
15350 : [doExeMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h01, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V True True True True True True True True False False False False False False False False > }, spec_bits: 'h000 }
|
||||
DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000000000000, write: True, capStore: False, potentialCapLoad: False }
|
||||
calling cycle
|
||||
18020 : [doFinishMem] DTlbResp { resp: <'h0000000000000000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, vaddr: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000000000000, check_high: 'h00000000000000008, check_inclusive: True } }, specBits: 'h000 }
|
||||
15360 : [doFinishMem] DTlbResp { resp: <'h0000000000000000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, vaddr: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000000000000, check_high: 'h00000000000000008, check_inclusive: True } }, specBits: 'h000 }
|
||||
calling cycle
|
||||
calling cycle
|
||||
calling cycle
|
||||
@@ -2010,46 +1753,44 @@ calling cycle
|
||||
calling cycle
|
||||
calling cycle
|
||||
calling cycle
|
||||
15580 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080006000, toState: E, child: , data: tagged Valid CLine { tag: <V False False False False >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > > }, id: 'h0 }
|
||||
calling cycle
|
||||
15590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040003, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: <V False False False False >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > > } }, repInfo: , setAuxData: tagged Invalid }
|
||||
15590 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs:
|
||||
15590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080006000, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 }
|
||||
15590 : [Ld resp] 'h02; TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }
|
||||
15590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False False False False >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > > } ; tagged Invalid
|
||||
calling cycle
|
||||
18260 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080006000, toState: E, child: , data: tagged Valid CLine { tag: <V False False False False >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > > }, id: 'h0 }
|
||||
15600 : [doRespLdMem] 'h02; TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'h0000000000000000 > } }
|
||||
[RFile] wr_ 3: r 5a <= 2aaaaaaaaaaaaaaa8aaa00001fffff44000000
|
||||
calling cycle
|
||||
18270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040003, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: <V False False False False >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > > } }, repInfo: , setAuxData: tagged Invalid }
|
||||
18270 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs:
|
||||
18270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080006000, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h803c }
|
||||
18270 : [Ld resp] 'h02; TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }
|
||||
18270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False False False False >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > > } ; tagged Invalid
|
||||
[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False }, paddr: 'h0000000080006000, isMMIO: False, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, fault: tagged Invalid , allowCap: False, killed: tagged Invalid }
|
||||
calling cycle
|
||||
18280 : [doRespLdMem] 'h02; TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'h0000000000000000 > } }
|
||||
[RFile] wr_ 3: r 58 <= 2aaaaaaaaaaaaaaa8aaa00001fffff44000000
|
||||
15620 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0c, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
instret:26 PC:0x1ffff0000000000000000000080000044 instr:0x0005b283 iType:Ld [doCommitNormalInst [0]] 1562
|
||||
instret:27 PC:0x1ffff0000000000000000000080000048 instr:0x10001337 iType:Alu [doCommitNormalInst [1]] 1562
|
||||
calling cycle
|
||||
[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False }, paddr: 'h0000000080006000, isMMIO: False, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, fault: tagged Invalid , allowCap: False, killed: tagged Invalid }
|
||||
[RFile] wr_ 1: r 5d <= 0000000020002000000000001fffff44000000
|
||||
15630 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0c, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
|
||||
instret:28 PC:0x1ffff000000000000000000008000004c instr:0x0000030e iType:Alu [doCommitNormalInst [0]] 1563
|
||||
calling cycle
|
||||
18300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0c, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
instret:24 PC:0x1ffff000000000000000000008000003c instr:0x0005b283 iType:Ld [doCommitNormalInst [0]] 1830
|
||||
instret:25 PC:0x1ffff0000000000000000000080000040 instr:0x10001337 iType:Alu [doCommitNormalInst [1]] 1830
|
||||
calling cycle
|
||||
[RFile] wr_ 1: r 5b <= 0000000020002000000000001fffff44000000
|
||||
18310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0c, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
|
||||
instret:26 PC:0x1ffff0000000000000000000080000044 instr:0x0000030e iType:Alu [doCommitNormalInst [0]] 1831
|
||||
calling cycle
|
||||
[RFile] wr_ 1: r 5d <= 0000000020002000000000001ffff800020000
|
||||
18320 : [doExeMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080008000 o: 'h0000000080008000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080008000 o: 'h0000000080008000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V True True True True True True True True False False False False False False False False > }, spec_bits: 'h000 }
|
||||
[RFile] wr_ 1: r 5f <= 0000000020002000000000001ffff800020000
|
||||
15640 : [doExeMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080008000 o: 'h0000000080008000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080008000 o: 'h0000000080008000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0c, rn2 'h0c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V True True True True True True True True False False False False False False False False > }, spec_bits: 'h000 }
|
||||
DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080008000, write: False, capStore: False, potentialCapLoad: False }
|
||||
instret:27 PC:0x1ffff0000000000000000000080000046 instr:0x2062865b iType:Cap [doCommitNormalInst [0]] 1832
|
||||
instret:28 PC:0x1ffff000000000000000000008000004a instr:0x00004321 iType:Alu [doCommitNormalInst [1]] 1832
|
||||
instret:29 PC:0x1ffff000000000000000000008000004e instr:0x2062865b iType:Cap [doCommitNormalInst [0]] 1564
|
||||
instret:30 PC:0x1ffff0000000000000000000080000052 instr:0x00004321 iType:Alu [doCommitNormalInst [1]] 1564
|
||||
calling cycle
|
||||
18330 : [doFinishMem] DTlbResp { resp: <'h0000000080008000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, vaddr: v: True a: 'h0000000080008000 o: 'h0000000080008000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080008000, check_high: 'h00000000080008008, check_inclusive: True } }, specBits: 'h000 }
|
||||
18330 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080008000, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, pcHash: 'h8050 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
|
||||
18330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080008000, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8050 }
|
||||
instret:29 PC:0x1ffff000000000000000000008000004c instr:0x1066065b iType:Cap [doCommitNormalInst [0]] 1833
|
||||
15650 : [doFinishMem] DTlbResp { resp: <'h0000000080008000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, vaddr: v: True a: 'h0000000080008000 o: 'h0000000080008000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080008000, check_high: 'h00000000080008008, check_inclusive: True } }, specBits: 'h000 }
|
||||
15650 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080008000, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, pcHash: 'h8058 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
|
||||
15650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080008000, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8058 }
|
||||
instret:31 PC:0x1ffff0000000000000000000080000054 instr:0x1066065b iType:Cap [doCommitNormalInst [0]] 1565
|
||||
calling cycle
|
||||
18340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False True False True >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > > } }, repInfo: , setAuxData: tagged Invalid }
|
||||
18340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080008000, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8050 }
|
||||
18340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace
|
||||
15660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False True False True >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > > } }, repInfo: , setAuxData: tagged Invalid }
|
||||
15660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080008000, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8058 }
|
||||
15660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace
|
||||
calling cycle
|
||||
calling cycle
|
||||
18360 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080008000, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8050 } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080008000, fromState: I, toState: E, canUpToE: True, id: 'h1, child: , isPrefetchRq: False }
|
||||
15680 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080008000, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8058 } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080008000, fromState: I, toState: E, canUpToE: True, id: 'h1, child: , isPrefetchRq: False }
|
||||
calling cycle
|
||||
calling cycle
|
||||
calling cycle
|
||||
@@ -2098,45 +1839,45 @@ calling cycle
|
||||
calling cycle
|
||||
calling cycle
|
||||
calling cycle
|
||||
18840 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080008000, toState: E, child: , data: tagged Valid CLine { tag: <V False False False False >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > > }, id: 'h1 }
|
||||
16160 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080008000, toState: E, child: , data: tagged Valid CLine { tag: <V False False False False >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > > }, id: 'h1 }
|
||||
calling cycle
|
||||
18850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: <V False False False False >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > > } }, repInfo: , setAuxData: tagged Invalid }
|
||||
18850 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs:
|
||||
18850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080008000, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8050 }
|
||||
18850 : [Ld resp] 'h03; TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }
|
||||
18850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False False False False >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > > } ; tagged Invalid
|
||||
16170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: <V False False False False >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > > } }, repInfo: , setAuxData: tagged Invalid }
|
||||
16170 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs:
|
||||
16170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080008000, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8058 }
|
||||
16170 : [Ld resp] 'h03; TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }
|
||||
16170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False False False False >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > > } ; tagged Invalid
|
||||
calling cycle
|
||||
18860 : [doRespLdMem] 'h03; TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'h0000000000000000 > } }
|
||||
[RFile] wr_ 3: r 5e <= 2aaaaaaaaaaaaaaa8aaa00001fffff44000000
|
||||
16180 : [doRespLdMem] 'h03; TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'h0000000000000000 > } }
|
||||
[RFile] wr_ 3: r 60 <= 2aaaaaaaaaaaaaaa8aaa00001fffff44000000
|
||||
calling cycle
|
||||
[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False }, paddr: 'h0000000080008000, isMMIO: False, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, fault: tagged Invalid , allowCap: False, killed: tagged Invalid }
|
||||
[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080008000, isMMIO: False, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, fault: tagged Invalid , allowCap: False, killed: tagged Invalid }
|
||||
calling cycle
|
||||
18880 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
instret:30 PC:0x1ffff0000000000000000000080000050 instr:0x00063283 iType:Ld [doCommitNormalInst [0]] 1888
|
||||
instret:31 PC:0x1ffff0000000000000000000080000054 instr:0x00080337 iType:Alu [doCommitNormalInst [1]] 1888
|
||||
16200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
instret:32 PC:0x1ffff0000000000000000000080000058 instr:0x00063283 iType:Ld [doCommitNormalInst [0]] 1620
|
||||
instret:33 PC:0x1ffff000000000000000000008000005c instr:0x00080337 iType:Alu [doCommitNormalInst [1]] 1620
|
||||
calling cycle
|
||||
[RFile] wr_ 0: r 62 <= 0000000020002400000000001fffff44000000
|
||||
18890 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
|
||||
instret:32 PC:0x1ffff0000000000000000000080000058 instr:0x00002325 iType:Alu [doCommitNormalInst [0]] 1889
|
||||
instret:33 PC:0x1ffff000000000000000000008000005a instr:0x00000332 iType:Alu [doCommitNormalInst [1]] 1889
|
||||
[RFile] wr_ 0: r 64 <= 0000000020002400000000001fffff44000000
|
||||
16210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
|
||||
instret:34 PC:0x1ffff0000000000000000000080000060 instr:0x00002325 iType:Alu [doCommitNormalInst [0]] 1621
|
||||
instret:35 PC:0x1ffff0000000000000000000080000062 instr:0x00000332 iType:Alu [doCommitNormalInst [1]] 1621
|
||||
calling cycle
|
||||
[RFile] wr_ 0: r 64 <= 0000000020002400100000001ffff804021000
|
||||
18900 : [doExeMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080009000 o: 'h0000000080009000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080009000 o: 'h0000000080009000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V True True True True True True True True False False False False False False False False > }, spec_bits: 'h000 }
|
||||
[RFile] wr_ 0: r 66 <= 0000000020002400100000001ffff804021000
|
||||
16220 : [doExeMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080009000 o: 'h0000000080009000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080009000 o: 'h0000000080009000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0d, rn2 'h0d, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V True True True True True True True True False False False False False False False False > }, spec_bits: 'h000 }
|
||||
DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080009000, write: False, capStore: False, potentialCapLoad: False }
|
||||
instret:34 PC:0x1ffff000000000000000000008000005c instr:0x206286db iType:Cap [doCommitNormalInst [0]] 1890
|
||||
instret:35 PC:0x1ffff0000000000000000000080000060 instr:0x00004321 iType:Alu [doCommitNormalInst [1]] 1890
|
||||
instret:36 PC:0x1ffff0000000000000000000080000064 instr:0x206286db iType:Cap [doCommitNormalInst [0]] 1622
|
||||
instret:37 PC:0x1ffff0000000000000000000080000068 instr:0x00004321 iType:Alu [doCommitNormalInst [1]] 1622
|
||||
calling cycle
|
||||
18910 : [doFinishMem] DTlbResp { resp: <'h0000000080009000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, vaddr: v: True a: 'h0000000080009000 o: 'h0000000080009000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080009000, check_high: 'h00000000080009008, check_inclusive: True } }, specBits: 'h000 }
|
||||
18910 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080009000, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, pcHash: 'h8066 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
|
||||
18910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080009000, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8066 }
|
||||
instret:36 PC:0x1ffff0000000000000000000080000062 instr:0x106686db iType:Cap [doCommitNormalInst [0]] 1891
|
||||
16230 : [doFinishMem] DTlbResp { resp: <'h0000000080009000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, vaddr: v: True a: 'h0000000080009000 o: 'h0000000080009000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080009000, check_high: 'h00000000080009008, check_inclusive: True } }, specBits: 'h000 }
|
||||
16230 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080009000, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, pcHash: 'h806e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
|
||||
16230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080009000, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h806e }
|
||||
instret:38 PC:0x1ffff000000000000000000008000006a instr:0x106686db iType:Cap [doCommitNormalInst [0]] 1623
|
||||
calling cycle
|
||||
18920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False True False True >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > > } }, repInfo: , setAuxData: tagged Invalid }
|
||||
18920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080009000, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8066 }
|
||||
18920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace
|
||||
16240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False True False True >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > > } }, repInfo: , setAuxData: tagged Invalid }
|
||||
16240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080009000, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h806e }
|
||||
16240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace
|
||||
calling cycle
|
||||
calling cycle
|
||||
18940 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080009000, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8066 } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080009000, fromState: I, toState: E, canUpToE: True, id: 'h1, child: , isPrefetchRq: False }
|
||||
16260 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080009000, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h806e } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080009000, fromState: I, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False }
|
||||
calling cycle
|
||||
calling cycle
|
||||
calling cycle
|
||||
@@ -2185,44 +1926,44 @@ calling cycle
|
||||
calling cycle
|
||||
calling cycle
|
||||
calling cycle
|
||||
19420 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080009000, toState: E, child: , data: tagged Valid CLine { tag: <V False False False False >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > > }, id: 'h1 }
|
||||
16740 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080009000, toState: E, child: , data: tagged Valid CLine { tag: <V False False False False >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > > }, id: 'h0 }
|
||||
calling cycle
|
||||
19430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: <V False False False False >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > > } }, repInfo: , setAuxData: tagged Invalid }
|
||||
19430 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs:
|
||||
19430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080009000, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8066 }
|
||||
19430 : [Ld resp] 'h04; TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }
|
||||
19430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False False False False >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > > } ; tagged Invalid
|
||||
16750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: <V False False False False >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > > } }, repInfo: , setAuxData: tagged Invalid }
|
||||
16750 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs:
|
||||
16750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080009000, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h806e }
|
||||
16750 : [Ld resp] 'h04; TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }
|
||||
16750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False False False False >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > > } ; tagged Invalid
|
||||
calling cycle
|
||||
19440 : [doRespLdMem] 'h04; TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'h0000000000000000 > } }
|
||||
[RFile] wr_ 3: r 65 <= 2aaaaaaaaaaaaaaa8aaa00001fffff44000000
|
||||
16760 : [doRespLdMem] 'h04; TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'h0000000000000000 > } }
|
||||
[RFile] wr_ 3: r 67 <= 2aaaaaaaaaaaaaaa8aaa00001fffff44000000
|
||||
calling cycle
|
||||
[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False }, paddr: 'h0000000080009000, isMMIO: False, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, fault: tagged Invalid , allowCap: False, killed: tagged Invalid }
|
||||
[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False }, paddr: 'h0000000080009000, isMMIO: False, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, fault: tagged Invalid , allowCap: False, killed: tagged Invalid }
|
||||
calling cycle
|
||||
19460 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0e, rn2 'h0e, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
instret:37 PC:0x1ffff0000000000000000000080000066 instr:0x0006b283 iType:Ld [doCommitNormalInst [0]] 1946
|
||||
instret:38 PC:0x1ffff000000000000000000008000006a instr:0x40001337 iType:Alu [doCommitNormalInst [1]] 1946
|
||||
16780 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0e, rn2 'h0e, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
instret:39 PC:0x1ffff000000000000000000008000006e instr:0x0006b283 iType:Ld [doCommitNormalInst [0]] 1678
|
||||
instret:40 PC:0x1ffff0000000000000000000080000072 instr:0x40001337 iType:Alu [doCommitNormalInst [1]] 1678
|
||||
calling cycle
|
||||
[RFile] wr_ 0: r 68 <= 0000000020000800000000001fffff44000000
|
||||
19470 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0e, rn2 'h0e, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
|
||||
instret:39 PC:0x1ffff000000000000000000008000006e instr:0x00000306 iType:Alu [doCommitNormalInst [0]] 1947
|
||||
[RFile] wr_ 0: r 6a <= 0000000020000800000000001fffff44000000
|
||||
16790 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h0e, rn2 'h0e, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
|
||||
instret:41 PC:0x1ffff0000000000000000000080000076 instr:0x00000306 iType:Alu [doCommitNormalInst [0]] 1679
|
||||
calling cycle
|
||||
[RFile] wr_ 0: r 6a <= 0000000020000800200000001ffff808022000
|
||||
19480 : [doExeMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0e, rn2 'h0e, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V True True True True True True True True False False False False False False False False > }, spec_bits: 'h000 }
|
||||
[RFile] wr_ 1: r 6c <= 0000000020000800200000001ffff808022000
|
||||
16800 : [doExeMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0e, rn2 'h0e, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V True True True True True True True True False False False False False False False False > }, spec_bits: 'h000 }
|
||||
DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080002000, write: False, capStore: False, potentialCapLoad: False }
|
||||
instret:40 PC:0x1ffff0000000000000000000080000070 instr:0x2062875b iType:Cap [doCommitNormalInst [0]] 1948
|
||||
instret:41 PC:0x1ffff0000000000000000000080000074 instr:0x00004321 iType:Alu [doCommitNormalInst [1]] 1948
|
||||
instret:42 PC:0x1ffff0000000000000000000080000078 instr:0x2062875b iType:Cap [doCommitNormalInst [0]] 1680
|
||||
instret:43 PC:0x1ffff000000000000000000008000007c instr:0x00004321 iType:Alu [doCommitNormalInst [1]] 1680
|
||||
calling cycle
|
||||
19490 : [doFinishMem] DTlbResp { resp: <'h0000000080002000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, vaddr: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002000, check_high: 'h00000000080002008, check_inclusive: True } }, specBits: 'h000 }
|
||||
19490 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080002000, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, pcHash: 'h807a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
|
||||
19490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a }
|
||||
instret:42 PC:0x1ffff0000000000000000000080000076 instr:0x1067075b iType:Cap [doCommitNormalInst [0]] 1949
|
||||
16810 : [doFinishMem] DTlbResp { resp: <'h0000000080002000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, vaddr: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002000, check_high: 'h00000000080002008, check_inclusive: True } }, specBits: 'h000 }
|
||||
16810 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080002000, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, pcHash: 'h8082 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid } ; tagged ToCache
|
||||
16810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 }
|
||||
instret:44 PC:0x1ffff000000000000000000008000007e instr:0x1067075b iType:Cap [doCommitNormalInst [0]] 1681
|
||||
calling cycle
|
||||
19500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False True False True >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > > } }, repInfo: , setAuxData: tagged Invalid }
|
||||
19500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a }
|
||||
19500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace
|
||||
16820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False True False True >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > > } }, repInfo: , setAuxData: tagged Invalid }
|
||||
16820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 }
|
||||
16820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace
|
||||
calling cycle
|
||||
calling cycle
|
||||
19520 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a } ; L1CRqSlot { way: 'h2, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002000, fromState: I, toState: E, canUpToE: True, id: 'h2, child: , isPrefetchRq: False }
|
||||
16840 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 } ; L1CRqSlot { way: 'h2, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002000, fromState: I, toState: E, canUpToE: True, id: 'h2, child: , isPrefetchRq: False }
|
||||
calling cycle
|
||||
calling cycle
|
||||
calling cycle
|
||||
@@ -2271,26 +2012,26 @@ calling cycle
|
||||
calling cycle
|
||||
calling cycle
|
||||
calling cycle
|
||||
20000 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002000, toState: E, child: , data: tagged Valid CLine { tag: <V False False False False >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > > }, id: 'h2 }
|
||||
17320 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002000, toState: E, child: , data: tagged Valid CLine { tag: <V False False False False >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000020000801 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > }, id: 'h2 }
|
||||
calling cycle
|
||||
20010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: <V False False False False >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > > } }, repInfo: , setAuxData: tagged Invalid }
|
||||
20010 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs:
|
||||
20010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807a }
|
||||
20010 : [Ld resp] 'h05; TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }
|
||||
20010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False False False False >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > > } ; tagged Invalid
|
||||
17330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: <V False False False False >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000020000801 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } }, repInfo: , setAuxData: tagged Invalid }
|
||||
17330 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs:
|
||||
17330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8082 }
|
||||
17330 : [Ld resp] 'h05; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }
|
||||
17330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False False False False >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000020000801 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } ; tagged Invalid
|
||||
calling cycle
|
||||
20020 : [doRespLdMem] 'h05; TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'h0000000000000000 > } }
|
||||
[RFile] wr_ 3: r 6b <= 2aaaaaaaaaaaaaaa8aaa00001fffff44000000
|
||||
17340 : [doRespLdMem] 'h05; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000 > } }
|
||||
[RFile] wr_ 3: r 6d <= 0000000000000000000000001fffff44000000
|
||||
calling cycle
|
||||
[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False }, paddr: 'h0000000080002000, isMMIO: False, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, fault: tagged Invalid , allowCap: False, killed: tagged Invalid }
|
||||
[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False }, paddr: 'h0000000080002000, isMMIO: False, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, fault: tagged Invalid , allowCap: False, killed: tagged Invalid }
|
||||
calling cycle
|
||||
instret:43 PC:0x1ffff000000000000000000008000007a instr:0x00073283 iType:Ld [doCommitNormalInst [0]] 2004
|
||||
instret:44 PC:0x1ffff000000000000000000008000007e instr:0x00004305 iType:Alu [doCommitNormalInst [1]] 2004
|
||||
instret:45 PC:0x1ffff0000000000000000000080000082 instr:0x00073283 iType:Ld [doCommitNormalInst [0]] 1736
|
||||
instret:46 PC:0x1ffff0000000000000000000080000086 instr:0x00004305 iType:Alu [doCommitNormalInst [1]] 1736
|
||||
calling cycle
|
||||
calling cycle
|
||||
[doDeqStQ_MMIO_issue] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000000000000, isMMIO: True, shiftedBE: <V True True True True True True True True False False False False False False False False >, stData: TaggedData { tag: False, data: <V 'h0000000000000001 'h0000000000000000 > }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8080 }; MMIOCRq { addr: 'h0000000000000000, func: tagged St , byteEn: <V True True True True True True True True False False False False False False False False >, data: TaggedData { tag: False, data: <V 'h0000000000000001 'h0000000000000000 > }, loadTags: False }
|
||||
[doDeqStQ_MMIO_issue] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000000000000, isMMIO: True, shiftedBE: <V True True True True True True True True False False False False False False False False >, stData: TaggedData { tag: False, data: <V 'h0000000000000001 'h0000000000000000 > }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8088 }; MMIOCRq { addr: 'h0000000000000000, func: tagged St , byteEn: <V True True True True True True True True False False False False False False False False >, data: TaggedData { tag: False, data: <V 'h0000000000000001 'h0000000000000000 > }, loadTags: False }
|
||||
calling cycle
|
||||
calling cycle
|
||||
calling cycle
|
||||
2010: mmioPlatform.rl_tohost: 0x1 (= 1)
|
||||
1742: mmioPlatform.rl_tohost: 0x1 (= 1)
|
||||
PASS
|
||||
|
||||
@@ -806,7 +806,7 @@ module mkCore#(CoreId coreId)(Core);
|
||||
iTlb.updateVMInfo(vmI);
|
||||
dTlb.updateVMInfo(vmD);
|
||||
l2Tlb.updateVMInfo(vmI, vmD);
|
||||
// $display ("%0d: %m.rule prepareCachesAndTlbs: updating VMInfo", cur_cycle);
|
||||
$display ("%0d: %m.rule prepareCachesAndTlbs: updating VMInfo", cur_cycle);
|
||||
end
|
||||
endrule
|
||||
|
||||
|
||||
Reference in New Issue
Block a user