49 lines
1.2 KiB
ArmAsm
49 lines
1.2 KiB
ArmAsm
.section .data
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.align 12
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# Root Table (L2)
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# Since we map 1GiB, this is the ONLY table we need.
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l2_table:
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.quad 0
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.quad 0
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# Entry 2 maps 0x80000000 - 0xBFFFFFFF
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# PPN 0x80000, Flags: D A G U R W X V (0xCF)
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.quad (0x80000 << 10) | 0xCF
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.fill 509, 8, 0
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.section .text
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.globl _start
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.align 4
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_start:
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# 1. Get the address of our table
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cllc ca0, l2_table
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cgetaddr t0, ca0
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# 2. Convert address to PPN
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srli t0, t0, 12
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# 3. Construct SATP with Mode 8 (Sv39)
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# The FIXME suggests bit 63 must be 1.
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li t1, 8
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slli t1, t1, 60
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or t0, t0, t1 # t0 = (8 << 60) | PPN
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# 4. Critical Write Sequence
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sfence.vma # Flush before enabling
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csrw sptbr, t0 # Write to SATP
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sfence.vma # Flush after enabling
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# 5. Transition to Virtual Space
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# We load an address from the .data section (0x80002000)
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# If paging is ON, the DTLB trace should now show (sv39)
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li t1, 0x80002000
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cspecialr ca1, pcc
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csetaddr ca1, ca1, t1
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ld t2, 0(ca1) # Trigger a DTLB lookup
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# 6. Exit / Finish
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# (Assuming your tohost logic)
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li t1, 1
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csd t1, 0(c1)
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loop: j loop |