Cheri-research/Toooba
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Minor tweaks, mostly cosmetic and $displays

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This commit is contained in:
rsnikhil
2020-02-06 14:15:56 -05:00
parent 8e0f0afb85
commit c14c9b3e6c
6 changed files with 647 additions and 681 deletions
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608
builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkCore.v
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File diff suppressed because it is too large Load Diff

2
builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkCoreW.v
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@@ -2271,7 +2271,7 @@ module mkCoreW(RST_N_dm_power_on_reset,
v__h6484 = v__h6490 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (EN_start)
$display("%0d: %m.method start: proc.start (pc %0d, tohostAddr %0h, fromhostAddr %0h)",
$display("%0d: %m.method start: proc.start (pc %0h, tohostAddr %0h, fromhostAddr %0h)",
v__h6484,
64'h0000000000001000,
start_tohost_addr,

677
builds/RV64ACDFIMSU_Toooba_verilator/Verilog_RTL/mkProc.v
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File diff suppressed because it is too large Load Diff

6
src_Core/Core/CoreW.bsv
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@@ -318,6 +318,12 @@ module mkCoreW #(Reset dm_power_on_reset)
AXI4_Master_IFC #(Wd_Id, Wd_Addr, Wd_Data, Wd_User)
dm_master_local = dummy_AXI4_Master_ifc;
`ifdef INCLUDE_TANDEM_VERIF
// TV, no DM: stub out the dm input to TV
Get #(Trace_Data) gs = getstub;
mkConnection (tv_encode.dm_in, gs);
`endif
`endif // for ifdef INCLUDE_GDB_CONTROL

6
src_Core/Core/Trace_Data2_to_Trace_Data.bsv
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@@ -45,6 +45,7 @@ endinterface
// ================================================================
(* synthesize *)
module mkTrace_Data2_to_Trace_Data (Trace_Data2_to_Trace_Data_IFC);
Integer verbosity = 0; // for debugging
@@ -116,13 +117,14 @@ module mkTrace_Data2_to_Trace_Data (Trace_Data2_to_Trace_Data_IFC);
rule rl_xform;
Trace_Data2 td2 <- pop (f_in);
match { .serialnum, .td } <- fav_xform (td2);
f_out.enq (tuple2 (serialnum, td));
if (verbosity != 0)
$display ("%0d: %m.rl_xform: serialnum:%0d PC:0x%0h instr:0x%08h",
cur_cycle, td2.serialnum, td2.pc, td2.orig_inst,
" iType:", fshow (td2.iType));
match { .serialnum, .td } <- fav_xform (td2);
f_out.enq (tuple2 (serialnum, td));
endrule
// ================================================================

29
src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv
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@@ -182,7 +182,6 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
inIfc.v_to_TV [way].put (x);
endaction
endfunction
`endif
// func units
@@ -467,10 +466,6 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
});
commitTrap <= commitTrap_val;
`ifdef INCLUDE_TANDEM_VERIF
fa_to_TV (rg_serialnum, x, 0);
`endif
if (verbosity >= 1) begin
$display ("instret:%0d PC:0x%0h instr:0x%08h", rg_serialnum, x.pc, x.orig_inst,
" iType:", fshow (x.iType), " [doCommitTrap]");
@@ -480,6 +475,11 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
$display ("CommitStage.doCommitTrap_flush: commitTrap: ", fshow (commitTrap_val));
end
`ifdef INCLUDE_TANDEM_VERIF
fa_to_TV (rg_serialnum, x, 0);
`endif
rg_serialnum <= rg_serialnum + 1;
// flush everything. Only increment epoch and stall fetch when we haven
// not done it yet (we may have already done them at rename stage)
inIfc.killAll;
@@ -627,17 +627,17 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
rob.deqPort[0].deq;
let x = rob.deqPort[0].deq_data;
`ifdef INCLUDE_TANDEM_VERIF
fa_to_TV (rg_serialnum, x, 0);
`endif
if(verbose) $display("[doCommitSystemInst] ", fshow(x));
if (verbosity >= 1) begin
$display("instret:%0d PC:0x%0h instr:0x%08h", rg_serialnum, x.pc, x.orig_inst,
" iType:", fshow (x.iType), " [doCommitSystemInst]");
rg_serialnum <= rg_serialnum + 1;
end
`ifdef INCLUDE_TANDEM_VERIF
fa_to_TV (rg_serialnum, x, 0);
`endif
rg_serialnum <= rg_serialnum + 1;
// we claim a phy reg for every inst, so commit its renaming
regRenamingTable.commit[0].commit;
@@ -795,17 +795,16 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage);
stop = True;
end
else begin
`ifdef INCLUDE_TANDEM_VERIF
fa_to_TV (rg_serialnum + instret, x, i);
`endif
if (verbose) $display("[doCommitNormalInst - %d] ", i, fshow(inst_tag), " ; ", fshow(x));
if (verbosity >= 1) begin
$display("instret:%0d PC:0x%0h instr:0x%08h", rg_serialnum + instret, x.pc, x.orig_inst,
" iType:", fshow (x.iType), " [doCommitNormalInst [%0d]]", i);
instret = instret + 1;
end
`ifdef INCLUDE_TANDEM_VERIF
fa_to_TV (rg_serialnum + instret, x, i);
`endif
instret = instret + 1;
// inst can be committed, deq it
rob.deqPort[i].deq;