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Experimentally remove repeated write of rg_m_halt_req register.

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jon
2021-06-25 17:31:10 +01:00
parent 4a50ae5bc8
commit b48a161fda
1 changed files with 0 additions and 2 deletions
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src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv
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@@ -324,8 +324,6 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage);
);
fetchStage.pipelines[0].deq;
`ifdef INCLUDE_GDB_CONTROL
fa_step_check;
if (verbosity >= 1) begin
if (firstTrap == tagged Valid (tagged Interrupt intrDebugHalt))
$display ("%0d: %m.renameStage.doRenaming_Trap: intrDebugHalt", cur_cycle);