Include xCHERI in ARCH and build directory names

Also use RVFI_DII not RVFIDII in the directory names. This makes everything match Piccolo/Flute rather than having Toooba be a weird, inconsistent and plain wrong.
2020-07-05 21:41:28 +01:00
parent 46ae8ea159
commit badf5c8e37
8 changed files with 4 additions and 4 deletions
--- a/builds/RV64ACDFIMSUxCHERI_Toooba_RVFI_DII_verilator/Makefile
+++ b/builds/RV64ACDFIMSUxCHERI_Toooba_RVFI_DII_verilator/Makefile
@@ -20,7 +20,7 @@ ALL_RISCY_DIRS = $(RISCY_DIRS):$(CONNECTAL_DIRS):$(RVFI_DII_DIRS):$(CHERI_DIRS)
 # ================================================================

 REPO ?= ../..
-ARCH ?= RV64ACDFIMSU
+ARCH ?= RV64ACDFIMSUxCHERI

 # ================================================================
 # RISC-V config macros passed into Bluespec 'bsc' compiler
--- a/builds/RV64ACDFIMSUxCHERI_Toooba_RVFI_DII_verilator/Mem.hex
+++ b/builds/RV64ACDFIMSUxCHERI_Toooba_RVFI_DII_verilator/Mem.hex
--- a/builds/RV64ACDFIMSUxCHERI_Toooba_RVFI_DII_verilator/TagTableStructure.bsv
+++ b/builds/RV64ACDFIMSUxCHERI_Toooba_RVFI_DII_verilator/TagTableStructure.bsv
--- a/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/Makefile
+++ b/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/Makefile
@@ -18,7 +18,7 @@ ALL_RISCY_DIRS = $(RISCY_DIRS):$(CONNECTAL_DIRS):$(CHERI_DIRS)
 # ================================================================

 REPO ?= ../..
-ARCH ?= RV64ACDFIMSU
+ARCH ?= RV64ACDFIMSUxCHERI

 # ================================================================
 # RISC-V config macros passed into Bluespec 'bsc' compiler
--- a/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/TagTableStructure.bsv
+++ b/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/TagTableStructure.bsv
--- a/builds/RV64ACDFIMSUxCHERI_Toooba_verilator/Makefile
+++ b/builds/RV64ACDFIMSUxCHERI_Toooba_verilator/Makefile
@@ -18,7 +18,7 @@ ALL_RISCY_DIRS = $(RISCY_DIRS):$(CONNECTAL_DIRS):$(CHERI_DIRS)
 # ================================================================

 REPO ?= ../..
-ARCH ?= RV64ACDFIMSU
+ARCH ?= RV64ACDFIMSUxCHERI

 # ================================================================
 # RISC-V config macros passed into Bluespec 'bsc' compiler
--- a/builds/RV64ACDFIMSUxCHERI_Toooba_verilator/TagTableStructure.bsv
+++ b/builds/RV64ACDFIMSUxCHERI_Toooba_verilator/TagTableStructure.bsv
--- a/src_SSITH_P3/Makefile
+++ b/src_SSITH_P3/Makefile
@@ -16,7 +16,7 @@ compile: compile_sim compile_synth
 # ================================================================

 REPO ?= ..
-ARCH ?= RV64ACDFIMSU
+ARCH ?= RV64ACDFIMSUxCHERI

 # ================================================================
 # RISC-V config macros passed into Bluespec 'bsc' compiler