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Did more cleaning up

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This commit is contained in:
Franz Fuchs
2021-09-06 15:55:28 +01:00
parent 4c9d89e936
commit bc7eed67ab
7 changed files with 5 additions and 96 deletions
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2
src_Core/CPU/CsrFile.bsv
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@@ -40,7 +40,6 @@
`include "ProcConfig.bsv"
import Types::*;
import ProcTypes::*;
import StatCounters::*;
import DefaultValue::*;
import ConcatReg::*;
import ConfigReg::*;
@@ -61,6 +60,7 @@ import Cur_Cycle :: *;
`ifdef PERFORMANCE_MONITORING
import PerformanceMonitor :: *;
import StatCounters::*;
`endif
// ================================================================

20
src_Core/RISCY_OOO/coherence/src/CCTypes.bsv
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@@ -45,26 +45,6 @@ import Connectable::*;
import GetPut::*;
import ClientServer::*;
//`ifdef PERFORMANCE_MONITORING
//typedef struct {
// Bit#(8) evt_LD;
// Bit#(8) evt_LD_MISS;
// Bit#(8) evt_LD_MISS_LAT;
// Bit#(8) evt_ST;
// Bit#(8) evt_ST_MISS;
// Bit#(8) evt_ST_MISS_LAT; // Unimplemented
// Bit#(8) evt_AMO;
// Bit#(8) evt_AMO_MISS;
// Bit#(8) evt_AMO_MISS_LAT;
// Bit#(8) evt_TLB;
// Bit#(8) evt_TLB_MISS; // Only leaf is stored in TLB thus a full
// Bit#(8) evt_TLB_MISS_LAT; // walk must happen every miss
// Bit#(8) evt_TLB_FLUSH;
// Bit#(8) evt_EVICT;
//} EventsCache deriving (Bits, FShow);
//typedef TDiv#(SizeOf#(EventsCache),8) EventsCacheElements;
//`endif
typedef enum {
I = 2'd0,
S = 2'd1,

2
src_Core/RISCY_OOO/coherence/src/IBank.bsv
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@@ -60,8 +60,8 @@ import RandomReplace::*;
`ifdef PERFORMANCE_MONITORING
import PerformanceMonitor::*;
import BlueUtils::*;
`endif
import StatCounters::*;
`endif
export ICRqStuck(..);
export IPRqStuck(..);

2
src_Core/RISCY_OOO/coherence/src/L1Bank.bsv
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@@ -62,9 +62,9 @@ import LatencyTimer::*;
import RandomReplace::*;
`ifdef PERFORMANCE_MONITORING
import PerformanceMonitor::*;
import StatCounters::*;
import BlueUtils::*;
`endif
import StatCounters::*;
export L1CRqStuck(..);
export L1PRqStuck(..);

2
src_Core/RISCY_OOO/coherence/src/LLBank.bsv
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@@ -53,9 +53,9 @@ import ConfigReg::*;
import RandomReplace::*;
`ifdef PERFORMANCE_MONITORING
import PerformanceMonitor::*;
import StatCounters::*;
import BlueUtils::*;
`endif
import StatCounters::*;
export LLCRqStuck(..);
export LLBank(..);

2
src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv
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@@ -72,9 +72,9 @@ import CacheUtils::*;
`ifdef PERFORMANCE_MONITORING
import PerformanceMonitor::*;
import BlueUtils::*;
import StatCounters::*;
import DReg::*;
`endif
import StatCounters::*;
import Cur_Cycle :: *;

71
src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv
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@@ -1049,81 +1049,10 @@ endfunction
function x addPc(x cap, Bit#(12) inc) provisos (Add#(f, 12, c), CHERICap::CHERICap#(x, a, b, c, d, e)) = setAddrUnsafe(cap, getAddr(cap) + signExtend(inc));
`ifdef PERFORMANCE_MONITORING
//`ifdef CONTRACTS_VERIFY
//typedef 128 No_Of_Evts;
//`else
//typedef 112 No_Of_Evts;
//`endif
typedef 8 Report_Width;
typedef 64 Counter_Width;
typedef 29 No_Of_Ctrs;
//typedef struct {
// SupCnt evt_REDIRECT;
// SupCnt evt_TRAP;
// SupCnt evt_BRANCH;
// SupCnt evt_JAL;
// SupCnt evt_JALR;
// SupCnt evt_AUIPC;
// SupCnt evt_LOAD;
// SupCnt evt_STORE;
// SupCnt evt_LR;
// SupCnt evt_SC;
// SupCnt evt_AMO;
// SupCnt evt_SERIAL_SHIFT;
// SupCnt evt_INT_MUL_DIV_REM;
// SupCnt evt_FP;
// SupCnt evt_SC_SUCCESS;
// SupCnt evt_LOAD_WAIT;
// SupCnt evt_STORE_WAIT;
// SupCnt evt_FENCE;
// SupCnt evt_F_BUSY_NO_CONSUME; // XXX
// SupCnt evt_D_BUSY_NO_CONSUME; // XXX
// SupCnt evt_1_BUSY_NO_CONSUME; // XXX
// SupCnt evt_2_BUSY_NO_CONSUME; // XXX
// SupCnt evt_3_BUSY_NO_CONSUME; // XXX
// SupCnt evt_IMPRECISE_SETBOUND; // XXX
// SupCnt evt_UNREPRESENTABLE_CAP; // XXX
// SupCnt evt_MEM_CAP_LOAD;
// SupCnt evt_MEM_CAP_STORE;
// SupCnt evt_MEM_CAP_LOAD_TAG_SET;
// SupCnt evt_MEM_CAP_STORE_TAG_SET;
//} EventsCore deriving (Bits, FShow);
//typedef TDiv#(SizeOf#(EventsCore),SizeOf#(SupCnt)) EventsCoreElements;
//
//typedef Bit#(Report_Width) HpmRpt;
//typedef struct {
// HpmRpt evt_REDIRECT;
// HpmRpt evt_TRAP;
// HpmRpt evt_BRANCH;
// HpmRpt evt_JAL;
// HpmRpt evt_JALR;
// HpmRpt evt_AUIPC;
// HpmRpt evt_LOAD;
// HpmRpt evt_STORE;
// HpmRpt evt_LR;
// HpmRpt evt_SC;
// HpmRpt evt_AMO;
// HpmRpt evt_SERIAL_SHIFT;
// HpmRpt evt_INT_MUL_DIV_REM;
// HpmRpt evt_FP;
// HpmRpt evt_SC_SUCCESS;
// HpmRpt evt_LOAD_WAIT;
// HpmRpt evt_STORE_WAIT;
// HpmRpt evt_FENCE;
// HpmRpt evt_F_BUSY_NO_CONSUME; // XXX
// HpmRpt evt_D_BUSY_NO_CONSUME; // XXX
// HpmRpt evt_1_BUSY_NO_CONSUME; // XXX
// HpmRpt evt_2_BUSY_NO_CONSUME; // XXX
// HpmRpt evt_3_BUSY_NO_CONSUME; // XXX
// HpmRpt evt_IMPRECISE_SETBOUND; // XXX
// HpmRpt evt_UNREPRESENTABLE_CAP; // XXX
// HpmRpt evt_MEM_CAP_LOAD;
// HpmRpt evt_MEM_CAP_STORE;
// HpmRpt evt_MEM_CAP_LOAD_TAG_SET;
// HpmRpt evt_MEM_CAP_STORE_TAG_SET;
//} EventsCoreMem deriving (Bits, FShow); // Memory needs more space for reporting delays
//typedef TDiv#(SizeOf#(EventsCoreMem),Report_Width) EventsCoreMemElements;
typedef struct {
SupCnt evt_RENAMED_INST;