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Merge branch 'CHERI' into faf28_sbc_jumps

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This commit is contained in:
Franz Fuchs
2021-07-08 17:14:27 +01:00
parent 224ab35679 849d5c57f8
commit c37c611522
5 changed files with 7 additions and 9 deletions
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4
src_Core/CPU/CPU_Decode_C.bsv
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@@ -146,17 +146,17 @@ function Instr fv_decode_C (MISA misa, Bit #(2) xl, Bool cap_enc, Instr_C instr_
else if (valid_C_SUBW) instr = i_C_SUBW;
else if (valid_C_EBREAK) instr = i_C_EBREAK;
`ifdef RV64
else if (valid_C_LDSP) instr = i_C_LDSP;
else if (valid_C_SDSP) instr = i_C_SDSP;
else if (valid_C_LD) instr = i_C_LD;
else if (valid_C_SD) instr = i_C_SD;
`endif
`ifdef RV64
else if (valid_C_LQSP) instr = i_C_LQSP;
else if (valid_C_SQSP) instr = i_C_SQSP;
else if (valid_C_LQ) instr = i_C_LQ;
else if (valid_C_SQ) instr = i_C_SQ;
`endif
`ifdef ISA_F
else if (valid_C_FLWSP) instr = i_C_FLWSP;

2
src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
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@@ -624,7 +624,7 @@ module mkFetchStage(FetchStage);
doAssert(prev_frag.dii_pid+1 == frag.dii_pid, "Attached fragments with non-contigious DII IDs");
`endif
end
end else if (is_16b_inst(frag.inst_frag)) begin // 16-bit instruction
end else if (is_16b_inst(frag.inst_frag) || isValid(frag.cause)) begin // 16-bit instruction
new_pick = tagged Valid fetch3_2_instC(frag,
fv_decode_C (misa, misa_mxl_64, getFlags(decompressPc(frag.pc))==1, frag.inst_frag),
zeroExtend(frag.inst_frag));

2
src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv
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@@ -324,8 +324,6 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage);
);
fetchStage.pipelines[0].deq;
`ifdef INCLUDE_GDB_CONTROL
fa_step_check;
if (verbosity >= 1) begin
if (firstTrap == tagged Valid (tagged Interrupt intrDebugHalt))
$display ("%0d: %m.renameStage.doRenaming_Trap: intrDebugHalt", cur_cycle);

4
src_Core/RISCY_OOO/procs/lib/IndexedMultiset.bsv
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@@ -146,7 +146,7 @@ module mkIndexedMultisetQueue(IndexedMultiset#(Bit#(idxTSz), datT, remWidth))
Reg#(Bit#(TAdd#(idxTSz,1))) ltail <- mkReg(0);
idxT head = truncate(lhead);
Bit#(TAdd#(idxTSz,1)) level = lhead - ltail;
//Bool empty = (level==0);
Bool empty = (level==0);
Bool full = (level==fromInteger(valueOf(TExp#(idxTSz))));
Bool almostFull = (level>=fromInteger(valueOf(TExp#(idxTSz)))-1);
@@ -201,7 +201,7 @@ module mkIndexedMultisetQueue(IndexedMultiset#(Bit#(idxTSz), datT, remWidth))
method ActionValue#(IndexedMultisetIndices#(idxT)) insertAndReserve(datT ins, datT res) if (!almostFull);
idxT insIdx = head - 1; // Default, assuming a match.
idxT resIdx = head - 1; // Default, assuming a match.
if (recsRead[head - 1]!=ins) begin
if (recsRead[head - 1]!=ins || empty) begin
insIdx = head;
insertW.wset(ins); // Increment head.
if (res!=ins) begin

4
src_Core/RISCY_OOO/procs/lib/Map.bsv
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@@ -70,7 +70,7 @@ Bitwise#(ix), Eq#(ix), Arith#(ix));
Reg#(Bit#(TLog#(as))) wayNext <- mkReg(0);
Integer a = valueof(as);
Reg#(Bool) clearReg <- mkReg(False);
Reg#(Bool) clearReg <- mkReg(True);
Reg#(ix) clearCount <- mkReg(0);
PulseWire didUpdate <- mkPulseWire;
rule doClear(clearReg && !didUpdate);
@@ -137,7 +137,7 @@ Bitwise#(ix), Eq#(ix), Arith#(ix), PrimIndex#(ix, a__));
Reg#(Bit#(TLog#(as))) wayNext <- mkReg(0);
Integer a = valueof(as);
Reg#(Bool) clearReg <- mkReg(False);
Reg#(Bool) clearReg <- mkReg(True);
Reg#(ix) clearCount <- mkReg(0);
(* fire_when_enabled, no_implicit_conditions *)
rule updateCanon;