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Remove commented-out code.

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Enable building with open-source BSC.

Resolve a couple issues brought up by Jess.

Remove a stray space (as noted by Jess).
This commit is contained in:
jon
2021-01-08 12:20:53 +00:00
parent a6771219ba
commit c515fb4518
3 changed files with 6 additions and 27 deletions
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15
src_Core/CPU/MMIOPlatform.bsv
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@@ -48,7 +48,6 @@ import GetPut::*;
import ClientServer::*;
import Connectable::*;
import FIFOF :: *;
// import BRAMCore::*;
// ----------------
// BSV additional libs
@@ -937,19 +936,7 @@ module mkMMIOPlatform #(Vector#(CoreNum, MMIOCoreToPlatform) cores,
$display (" ", fshow (req));
end
endrule
/*
function Vector #(SupSizeX2, Maybe #(Instruction16)) prepareFinalInstResp(Vector #(SupSize, Maybe #(Instruction)) respBigInsts, Bit#(1) addr_bit_1);
Vector #(SupSizeX2, Maybe #(Instruction16)) respSmallInsts = replicate (Invalid);
for (Integer i = 0; i < valueOf (SupSize); i = i+1) begin
if (respBigInsts[i] matches tagged Valid .inst) begin
respSmallInsts[i*2] = tagged Valid (truncate(inst));
respSmallInsts[(i*2) + 1] = tagged Valid (truncateLSB(inst));
end
end
// This unconventional zero-extension of addr_bit_1 works around a type error in shiftOutFrom0.
return shiftOutFrom0(Invalid, respSmallInsts, {4'b0, addr_bit_1});
endfunction
*/
rule rl_mmio_from_fabric_ifetch_rsp (curReq matches tagged MMIO_Fabric_Adapter .addr
&&& (state == WaitResp)
&&& isInstFetch);

7
src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
View File

@@ -690,11 +690,10 @@ module mkFetchStage(FetchStage);
// do decode and branch prediction
// Drop here if does not match the decode_epoch.
// We predicted a taken branch for PC, but this is an
// uncompressed instruction, so we redirect to this PC and
// train it to fetch the other half in future.
if (in.decode_epoch == decode_epoch_local && in.mispred_first_half) begin
// We predicted a taken branch for PC, but this is an
// uncompressed instruction, so we redirect to this PC and
// train it to fetch the other half in future.
if (verbose) $display("mispredicted first half in decode: pc : %h", pc);
decode_epoch_local = !decode_epoch_local;
redirectPc = Valid (pc); // record redirect to the first PC in this bundle.

11
src_Core/RISCY_OOO/procs/lib/IndexedMultiset.bsv
View File

@@ -165,22 +165,17 @@ module mkIndexedMultisetQueue(IndexedMultiset#(Bit#(idxTSz), datT, remWidth))
Bit#(TAdd#(idxTSz,1)) nlhead = lhead;
Bit#(TAdd#(idxTSz,1)) nltail = ltail;
if (insertW.wget matches tagged Valid .d) begin
$display("insert dat:%x nlhead:%d", {pack(d),12'b0}, nlhead);
idxT i = truncate(nlhead);
recs[i] = d;
nlhead = nlhead + 1;
end
if (reserveW.wget matches tagged Valid .d) begin
$display("reserve dat:%x nlhead:%d", {pack(d),12'b0}, nlhead);
idxT i = truncate(nlhead);
recs[i] = d;
//nlhead = nlhead + 1;
end
for (Integer i = 0; i < valueOf(remWidth); i = i + 1)
if (removeW[i].wget matches tagged Valid .r) begin
$display("remove[%d] idx:%d", i, r);
if (removeW[i].wget matches tagged Valid .r)
nltail = updateWidePointer(nltail, r);
end
if (clearW) begin
nlhead = 0;
nltail = 0;
@@ -188,7 +183,6 @@ module mkIndexedMultisetQueue(IndexedMultiset#(Bit#(idxTSz), datT, remWidth))
lhead <= nlhead;
ltail <= nltail;
writeVReg(records, recs);
$display("full:%x ltail:%d lhead:%d level:%d", full, ltail, lhead, level);
endrule
Vector#(remWidth, IndexedMultisetRemoveIfc#(idxT)) removes;
@@ -210,11 +204,10 @@ module mkIndexedMultisetQueue(IndexedMultiset#(Bit#(idxTSz), datT, remWidth))
if (recsRead[head - 1]!=ins) begin
insIdx = head;
insertW.wset(ins); // Increment head.
resIdx = head; // new default for reserved.
if (res!=ins) begin
resIdx = head + 1;
reserveW.wset(res); // Increment head again!
end
end else resIdx = head;
end else if (recsRead[head - 1]!=res) begin
resIdx = head;
reserveW.wset(res);