Use only 20 bits of address on the AXI lite port

2024-07-08 17:12:47 +01:00
parent 02ee2bdee0
commit c766187368
1 changed files with 1 additions and 1 deletions
--- a/src_Core/Core/CoreW.bsv
+++ b/src_Core/Core/CoreW.bsv
@@ -120,7 +120,7 @@ import DM_CPU_Req_Rsp ::*;
 // The Core module

 typedef WindCoreMid #( // AXI lite subordinate control port parameters
-                       21, 32, 0, 0, 0, 0, 0
+                       20, 32, 0, 0, 0, 0, 0
                       // AXI manager 0 port parameters
                     , TAdd #(Wd_MId, 1), Wd_Addr, Wd_Data, 0, 0, 0, 0, 0
                       // AXI manager 1 port parameters