Use DReg instead of Reg, as intended.

This commit is contained in:
Jonathan Woodruff
2024-01-22 12:06:39 +00:00
parent b586937953
commit ca4e120a6c

View File

@@ -43,6 +43,7 @@ import ProcTypes::*;
import TlbTypes::*;
import Performance::*;
import FullAssocTlb::*;
import DReg::*;
import ConfigReg::*;
import Fifos::*;
import Cntrs::*;
@@ -249,7 +250,7 @@ module mkITlb(ITlb::ITlb);
no_pending_wire <= !isValid(miss);
endrule
Reg#(Bool) vm_info_change <- mkReg(False);
Reg#(Bool) vm_info_change <- mkDReg(False);
method Action flush if(!needFlush);
needFlush <= True;