Default to Data Cache Stride 2 prefetcher, and no Instruction Cache

prefetcher.

builds/Resources/Include_RISCY_Config.mk

@@ -45,10 +45,10 @@ SIM_LLC_ARBITER_LAT ?=
 # default check cache deadlock and rename error
 CHECK_DEADLOCK ?= true
 RENAME_DEBUG ?= false
-INSTR_PREFETCHER_LOCATION ?= L1
+INSTR_PREFETCHER_LOCATION ?= NONE
 INSTR_PREFETCHER_TYPE ?= SINGLE_WINDOW_TARGET
 DATA_PREFETCHER_LOCATION ?= L1
-DATA_PREFETCHER_TYPE ?= MARKOV_ON_HIT_2
+DATA_PREFETCHER_TYPE ?= STRIDE
 
 # clk frequency depends on core size
 ifneq (,$(filter $(CORE_SIZE),TINY SMALL BOOM MEDIUM))