Keep unaligned instruction fetch from breaking DII.

2020-07-17 16:39:13 +01:00
parent 4d2f971767
commit d7a4d3497b
1 changed files with 3 additions and 0 deletions
--- a/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
+++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
@@ -579,6 +579,9 @@ module mkFetchStage(FetchStage);
       */

        match { .posLastSupX2, .pred_next_pc } <- fav_pred_next_pc (pc);
+        `ifdef RVFI_DII
+            posLastSupX2 = 3;
+        `endif
        let next_fetch_pc = fromMaybe(addPc(pc, 2 * (fromInteger(posLastSupX2) + 1)), pred_next_pc);
        pc_reg[pc_fetch1_port] <= next_fetch_pc;