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LLC_AXI4_Adapter.bsv: Make more obviously correct

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Previously we were relying on the beat count registers being exactly the
right number of bits such that we'd overflow from 7 back to 0 after the
final flit. This change aligns the LLC adapter with the MMIO adapter,
which already does things in a safer way. We can also just look at rlast
for read respones rather than a full 3-bit comparison (the MMIO adapter
also makes this micro-optimisation).
This commit is contained in:
Jessica Clarke
2020-07-06 19:01:56 +01:00
parent c406d357c9
commit e9d212fcbc
1 changed files with 11 additions and 8 deletions
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19
src_Core/CPU/LLC_AXI4_Adapter.bsv
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@@ -154,7 +154,7 @@ module mkLLC_AXi4_Adapter #(MemFifoClient #(idT, childT) llc)
let new_cline = CLine { tag: rg_rd_rsp_beat[0] == 0 ? unpack(new_cline_tag) : rg_cline.tag
, data: unpack(new_cline_data) };
if (rg_rd_rsp_beat == 7) begin
if (mem_rsp.rlast) begin
let ldreq <- pop (f_pending_reads);
MemRsMsg #(idT, childT) resp = MemRsMsg {data: new_cline,
child: ldreq.child,
@@ -164,10 +164,13 @@ module mkLLC_AXi4_Adapter #(MemFifoClient #(idT, childT) llc)
if (cfg_verbosity > 1)
$display (" Response to LLC: ", fshow (resp));
end
rg_cline <= new_cline;
rg_rd_rsp_beat <= rg_rd_rsp_beat + 1;
rg_rd_rsp_beat <= 0;
rg_cline <= unpack(0);
end else begin
rg_rd_rsp_beat <= rg_rd_rsp_beat + 1;
rg_cline <= new_cline;
end
endrule
// ================================================================
@@ -204,8 +207,11 @@ module mkLLC_AXi4_Adapter #(MemFifoClient #(idT, childT) llc)
// on last flit...
// ===============
if (rg_wr_req_beat == 7)
if (rg_wr_req_beat == 7) begin
llc.toM.deq;
rg_wr_req_beat <= 0;
end else // increment flit counter
rg_wr_req_beat <= rg_wr_req_beat + 1;
// on each flit ...
// ================
@@ -217,9 +223,6 @@ module mkLLC_AXi4_Adapter #(MemFifoClient #(idT, childT) llc)
wstrb: line_strb[rg_wr_req_beat],
wlast: rg_wr_req_beat == 7,
wuser: pack(line_data[rg_wr_req_beat[2:1]].tag)});
// increment flit counter
rg_wr_req_beat <= rg_wr_req_beat + 1;
endrule
// ----------------