Cheri-research/Toooba
1
0
Fork 0
Code Issues 1 Pull Requests Actions Packages Projects Releases Wiki Activity

Put all dirs for source description in code blocks

Browse Source
This commit is contained in:
Marno van der Maas
2020-10-02 13:09:51 +01:00
committed by GitHub
parent 00ffdd7228
commit ed9541e8d0
1 changed files with 3 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
README.md
View File

@@ -93,10 +93,10 @@ library RTL can be found in the directory `src_bsc_lib_RTL`.
- `src_Core/`, for the CPU core, with sub-directories:
- `Core/`: the top-level of the CPU Core (specifically, the files CoreW_IFC.bsv and CoreW.bsv)
- 'CPU/': more CPU core sources
- 'RISCY_OOO': the bulk of the code, taken from MIT's riscy-ooo design, with local modifications.
- `CPU/`: more CPU core sources
- `RISCY_OOO`: the bulk of the code, taken from MIT's riscy-ooo design, with local modifications.
- `ISA/`: generic types/constants/functions for the RISC-V ISA (not CPU-implementation-specific)
- 'PLIC/': Platform-Level Interrupt Controller (standard RISC-V spec)
- `PLIC/`: Platform-Level Interrupt Controller (standard RISC-V spec)
- `BSV_Additional_Libs/`: generic utilities (not CPU-specific)
- `Debug_Module/`: RISC-V Debug Module to debug the CPU from GDB or other debuggers