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Experiment with a zero-cycle TLB in instruction fetch as well.

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This commit is contained in:
Jonathan Woodruff
2024-01-16 10:05:17 +00:00
parent 25a728b6d3
commit eee5a2c23b
2 changed files with 4 additions and 9 deletions
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2
src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
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@@ -414,7 +414,7 @@ module mkFetchStage(FetchStage);
endaction);
// Pipeline Stage FIFOs
Fifo#(2, Fetch1ToFetch2) f12f2 <- mkCFFifo;
Fifo#(2, Fetch1ToFetch2) f12f2 <- mkBypassFifo;
Fifo#(4, Fetch2ToFetch3) f22f3 <- mkCFFifo; // FIFO should match I$ latency
// These two fifos needs a capacity of 3 for full throughput if we fire only when we can enq on on channels.
SupFifo#(SupSizeX2, 3, Fetch3ToDecode) f32d <- mkUGSupFifo; // Unguarded to prevent the static analyser from exploding.

11
src_Core/RISCY_OOO/procs/lib/ITlb.bsv
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@@ -115,7 +115,7 @@ module mkITlb(ITlb::ITlb);
Reg#(Bool) waitFlushP <- mkReg(False);
// resp FIFO to proc
Fifo#(2, TlbResp) hitQ <- mkCFFifo;
Fifo#(2, TlbResp) hitQ <- mkBypassFifo;
// current processor VM information
Reg#(VMInfo) vm_info <- mkReg(defaultValue);
@@ -294,14 +294,9 @@ module mkITlb(ITlb::ITlb);
eparvm_info.sanctum_evmask = 0;
if ((vm_info.prv == prvM ? (outOfProtectionDomain(parvm_info,vaddr) && outOfProtectionDomain(eparvm_info,vaddr)) : outOfProtectionDomain(vm_info, vaddr))) begin
hitQ.enq(tuple2(?, Valid (excInstAccessFault)));
end
`else
// No security check
if (False) begin
noAction;
end
end else
`endif
else if (vm_info.sv39) begin
if (vm_info.sv39) begin
let vpn = getVpn(vaddr);
let trans_result = tlb.translate(vpn, vm_info.asid);
if (!validVirtualAddress(vaddr)) hitQ.enq(tuple3(?, Valid (excInstPageFault), False));