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Potential workaround for issue with vcu118 memory bus error.

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Just use the same ID for all outstanding requests such that all requests
are in-order.
Previously we were working fine with requests serialised; requests
are now fully pipelined and out-of-order.
This change should roll back to in-order, but still pipelined.
This only affects the top-level used in the GFE (vcu118).
This design is working on the DE10 setup, so the issue is not
believed fundamental with CoreW.
This commit is contained in:
Jonathan Woodruff
2024-04-04 14:09:16 +01:00
parent 6f8c371a5c
commit f86ea0203d
1 changed files with 5 additions and 1 deletions
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6
src_SSITH_P3/src_BSV/P3_Core.bsv
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@@ -340,9 +340,13 @@ module mkP3_Core (P3_Core_IFC);
// ================================================================
`endif
// Work around issue that is not understood with multiple outstanding
// requests in VCU118 GFE system.
let master0_inOrder <- mkAXI4SingleIDMaster(master_0_delay.master);
// ================================================================
// INTERFACE
let master0_sig <- toAXI4_Master_Sig (master_0_delay.master);
let master0_sig <- toAXI4_Master_Sig (master0_inOrder);
let master1_sig <- toAXI4_Master_Sig (master_1_delay.master);
// ----------------------------------------------------------------
// Core CPU interfaces