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Added first attempts for counting wild exceptions

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This commit is contained in:
Franz Fuchs
2021-06-25 15:44:29 +01:00
parent f83d7b1554
commit fec16f64c8
3 changed files with 27 additions and 4 deletions
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3
src_Core/CPU/Core.bsv
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@@ -1171,12 +1171,15 @@ module mkCore#(CoreId coreId)(Core);
EventsTransExe transExe = renameStage.events;
SupCnt wildJumps = 0;
SupCnt wildExceptions = 0;
for(Integer i = 0; i < valueof(AluExeNum); i = i+1) begin
let alu_events = coreFix.aluExeIfc[i].events;
wildJumps = wildJumps + alu_events.evt_WILD_JUMP;
wildExceptions = wildExceptions + alu_events.evt_WILD_EXCEPTION;
end
transExe.evt_WILD_JUMP = wildJumps;
transExe.evt_WILD_EXCEPTION = wildExceptions;
Vector #(16, Bit #(Report_Width)) trans_exe_evts_vec = to_large_vector (transExe);
let events = append (null_evt, core_evts_vec);

27
src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv
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@@ -59,6 +59,10 @@ import Bypass::*;
import CHERICap::*;
import CHERICC_Fat::*;
import ISA_Decls_CHERI::*;
`ifdef PERFORMANCE_MONITORING
import BlueUtils::*;
`endif
import Cur_Cycle :: *;
@@ -233,7 +237,7 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline);
Integer finishSendBypassPort = 1;
`ifdef PERFORMANCE_MONITORING
Reg#(EventsTransExe) events_reg <- mkDReg(unpack(0));
Array#(Reg#(EventsTransExe)) events_reg <- mkDRegOR(2, unpack(0));
`endif
`ifdef PERF_COUNT
@@ -308,7 +312,7 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline);
if((val != ppc_addr) && (ppc_addr != pc_addr + 2) && (ppc_addr != pc_addr + 4)) begin
$display("Wild direct jump: pc = ", fshow(pc), " ppc = ", fshow(ppc), " imm = ", fshow(imm));
events.evt_WILD_JUMP = 1;
events_reg <= events;
events_reg[1] <= events;
end
end
@@ -321,7 +325,7 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline);
if(!res_targets && !res_ret_targets && (ppc_addr != pc_addr + 2) && (ppc_addr != pc_addr + 4)) begin
$display("Wild indirect jump: pc = ", fshow(pc), " ppc = ", fshow(ppc));
events.evt_WILD_JUMP = 1;
events_reg <= events;
events_reg[1] <= events;
end
end
`endif
@@ -439,6 +443,21 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline);
`endif
);
`ifdef PERFORMANCE_MONITORING
// get PC and PPC
let pc = getAddr(x.controlFlow.pc);
let ppc = getAddr(x.controlFlow.nextPc);
let validPc = x.isCompressed ? (pc + 2) : (pc + 4);
$display("spec_excps: pc = ", fshow(pc), ", ppc = ", fshow(ppc), ", validPc = ", fshow(validPc));
$display("capException = ", fshow(x.capException));
if(x.capException matches tagged Valid .exc &&& (ppc != validPc)) begin
$display("Wild exception");
EventsTransExe events = unpack(0);
events.evt_WILD_EXCEPTION = 1;
events_reg[0] <= events;
end
`endif
// handle spec tags for branch predictions
// TODO what happens here if we trap?
(* split *)
@@ -513,7 +532,7 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline);
endmethod
`ifdef PERFORMANCE_MONITORING
method events = events_reg;
method events = events_reg[0];
`endif
endmodule

1
src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv
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@@ -1124,6 +1124,7 @@ typedef TDiv#(SizeOf#(EventsCoreMem),Report_Width) EventsCoreMemElements;
typedef struct {
SupCnt evt_RENAMED_INST;
SupCnt evt_WILD_JUMP;
SupCnt evt_WILD_EXCEPTION;
} EventsTransExe deriving (Bits, FShow);
typedef TDiv#(SizeOf#(EventsTransExe),SizeOf#(SupCnt)) EventsTransExeElements;
`endif