dmactive should only go low when the debug module has successfully
reset. Approximate this by waiting for 1024 cycles, allowing any
register access requests and system bus requests to come back.
When DEBUG_WEDGE is defined, expose the last committed and next in the
reorder buffer PC and corresponding instruction via DMI registers, since
even when the core is wedged and we can't read GPRs etc we can still
interact with the debug module itself. Hopefully this proves useful for
debugging wedges.
