ab1e2385f9
ported over working malloc
2026-04-08 23:18:33 +01:00
e05b3a19f8
tried compiling with cheri mode
2026-03-30 14:05:05 +01:00
a6decda220
added working paging small kernel
2026-03-29 17:59:39 +01:00
4cea0232d4
pushed comparitive benchmark Toooba
2026-03-20 13:37:31 +00:00
9e82350306
added sample assembler bump allocator test
2026-02-02 16:26:23 +00:00
bf7bd16c53
adding current changes
2026-01-14 15:29:03 +00:00
c1cf362c70
changes
2026-01-10 16:14:01 +00:00
dd3336a2e0
added test for adding pages
2026-01-06 14:55:05 +00:00
6cc929d50a
added tracker to start
2025-12-24 13:12:11 +00:00
27aa16a7bf
added todo
2025-12-24 10:48:04 +00:00
28abd5de95
test traces and log file for TLB check
2025-12-23 09:34:06 +00:00
8242b86e2b
changed git modules
2025-12-01 19:43:08 +00:00
0f5520ea68
changes test benchmark
2025-12-01 19:41:40 +00:00
Jessica Clarke
a8299cfc01
CCTypes: Fix misleading bit width for MESI/Msi enum
...
4 does not fit in 2 bits. This appears to not matter in practice, as a
spot check of the generated Verilog shows 3'dN for state-related
constants, but we should not be relying on this surprisingly lax
behaviour from bsc, and who knows if there are ways in which bsc does
end up using the as-written bit width somewhere.
Fixes: 6d4644ce73
2025-11-02 14:28:02 +00:00
Rishiyur S. Nikhil
8fc12c1dee
Merge pull request #36 from h-chal/fix_rv64mi-p-access
...
fix: cache full virtual address for TLB micro-cache
(cherry picked from commit a79a4502c0e689058e6a2ffafd75b507c57ed3b9)
2025-10-31 18:07:27 +00:00
PeterRugg
ed011ac0fe
Fix unseal check operand order
2025-10-01 14:48:46 +01:00
Jonathan Woodruff
e576a2cae7
Revert "Changes to make Prefetcher more deterministic, and also to report schedules."
...
This reverts commit f964e1dd2c
2025-07-03 11:47:00 +01:00
Jonathan Woodruff
86c1c65261
Revert "Give commit redirect priority over branch/execute redirect."
...
This reverts commit 7bc17965b6
2025-07-03 11:46:43 +01:00
Jonathan Woodruff
d8d7fc3d2b
Revert "Improve scheduling of Reorder buffer. This includes an experimental relaxation of ordering."
...
This reverts commit 1873702c81
2025-07-03 10:39:52 +01:00
Jonathan Woodruff
79556da485
Revert "Get this building, removing scheduling issue."
...
This reverts commit 5331162e3c
2025-07-03 10:37:35 +01:00
Jonathan Woodruff
78c457cdd9
Bump benchmarks subrepo to fully independent version.
2025-07-01 16:10:21 +01:00
Jonathan Woodruff
acbf07ddf0
Merge pull request #46 from CTSRD-CHERI/CHERI-benchmarks
...
Cheri benchmarks
2025-06-12 10:15:45 +01:00
Jonathan Woodruff
16de32f2d4
Turn off RVFI for the benchmarks branch, as it affects CPI for some reason.
2025-06-06 14:33:55 +01:00
Jonathan Woodruff
824b575dc5
Add benchmarks directory and add script to run benchmarks in it.
2025-06-06 14:33:55 +01:00
Yuecheng-CAM
8af3b2e85a
Revert "initial commit, test compiled and run sucessfully"
...
This reverts commit d025278195
2025-06-01 18:17:24 +01:00
Yuecheng-CAM
d025278195
initial commit, test compiled and run sucessfully
2025-06-01 18:14:19 +01:00
Jonathan Woodruff
5331162e3c
Get this building, removing scheduling issue.
2025-05-23 10:43:42 +01:00
Jonathan Woodruff
1873702c81
Improve scheduling of Reorder buffer. This includes an experimental relaxation of ordering.
2025-05-20 16:37:34 +01:00
Jonathan Woodruff
7bc17965b6
Give commit redirect priority over branch/execute redirect.
2025-05-20 16:34:45 +01:00
Jonathan Woodruff
f964e1dd2c
Changes to make Prefetcher more deterministic, and also to report schedules.
2025-05-20 16:32:33 +01:00
Jonathan Woodruff
852d352d04
Merge pull request #45 from CTSRD-CHERI/CHERI-cachefix
...
Cheri cachefix
2025-05-20 11:36:56 +01:00
Jonathan Woodruff
63f25fb0ff
Enable > ways MSHRs by default.
2025-03-25 09:59:35 +00:00
Louis Hobson
769a6aec83
merge fix in L1Pipe
2025-03-25 09:23:08 +00:00
Louis Hobson
0c634fc019
Better print statements
2025-03-25 09:23:08 +00:00
Louis Hobson
04ee741ce2
Increase DCRqNum for test
2025-03-25 09:23:08 +00:00
Louis Hobson
a08a701805
Let cRqNum increase
2025-03-25 09:23:07 +00:00
Louis Hobson
c28c6c3670
Fix bad IBank merge
2025-03-25 09:23:07 +00:00
Louis Hobson
657e7e529b
Turn verbose on
2025-03-25 09:23:07 +00:00
Louis Hobson
535d85ff35
Request queues in L1 cache
2025-03-25 09:23:06 +00:00
Jonathan Woodruff
03b8face1e
Fix mac build more generically and cleaner.
2025-03-10 17:11:33 +00:00
Peter Rugg
8dd73525de
Add timer mapping for VCU118 builds
2025-02-20 17:45:58 +00:00
Franz Fuchs
6ebe612ff8
Fix Toooba to use addresses instead of offsets ( #32 )
...
* Fixed the Decoding of (C)JAL
* Use CSR addresses instead of offsets
* Fixed offsets correctly
* Fixed all offsets I could spot
* Fix use of modifyOffset function
* Corrected brAddrCalc function
* Preliminary fix for ddc offsetting
* Use setAddr instead of incOffset for DDC
* Deleted unnecessarily added lines in ALU pipeline
* Deleted white space
* Switched off verbosity for ALU pipeline
* Removed unnecessary print import
2025-02-05 11:06:07 +00:00
Franz Fuchs
5dea27457a
Corrected setting of global bit when unsealing
2025-01-27 16:13:56 +00:00
Franz Fuchs
d629d678e3
Fixed unseal bug
2025-01-27 16:13:56 +00:00
Peter Rugg
8d0f985d99
Ban illegal shift immediate encodings
2025-01-23 12:39:46 +00:00
Peter Rugg
773d5c1107
Implement CSetHigh
2025-01-22 16:07:06 +00:00
Yuecheng-CAM
f71a3d61a9
implement C_GET_HIGH
2025-01-22 16:05:41 +00:00
Jonathan Woodruff
6ffde560b5
Some small timing optimistations in the direction predictor, and also a new optional smaller configuration for the tournament predictor.
2025-01-21 10:09:06 +00:00
Peter Rugg
6f30f2b703
Fix floating point illegal handling
...
As well as clarifying the logic in the main decode function (no
functionality change), this also fixes some cases that should be
illegal but weren't caught in the memory instructions.
2025-01-20 17:18:54 +00:00
Peter Rugg
3fd8f22f66
Fix many illegal instruction decode cases
...
The decode had a TODO to handle illegal instructions more precisely.
Some instructions in the new CHERI spec were not causing traps, and
seemed to wedge the core.
Switch to a new style where instructions are assumed illegal unless
explicitly declared legal.
This definitely at least covers many funct3 etc fields where only
some of the encodings are currently used.
2025-01-20 17:18:54 +00:00
