Peter Rugg
8778369fe5
Merge remote-tracking branch 'upstream/master' into CHERI
2020-06-17 13:01:41 +01:00
Peter Rugg
4f4bbbbdcb
Add new TagController parameters to synth makefile
2020-06-17 11:40:23 +01:00
Peter Rugg
962ade1092
Fixes for synthesis
2020-06-05 17:40:28 +01:00
Peter Rugg
046319b909
Remove Tandem verification
2020-06-03 22:28:31 +01:00
rsnikhil
a6a227ed66
Incorporated patches/additions from Joe Stoy after GFE debugging (w. amendment ...)
...
Amendment: RegUNInit.v updated, removing an extraneous RST line.
2020-03-13 16:38:54 -04:00
Niraj N Sharma
6f5d079e7c
Modified synth and sim compile options in the Makefile
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Regenerated synth and sim RTLs
2020-02-22 17:51:13 +05:30
Niraj Sharma
568f52fc0b
Corrected typo in src_SSITH_P3 Makefile
2020-02-14 21:52:20 -05:00
Niraj Sharma
a99f046cdc
Regenerated RTL in src_SSITH_P3 with TANDEM_VERIF
2020-02-12 09:24:33 +05:30
Niraj Sharma
e35c48efff
Merged src_SSITH_P3 and src_SSITH_P3_sim
2020-02-07 21:00:50 +05:30
rsnikhil
4a7dd01023
Removed -D EXTERNAL_DEBUG_MODULE in src_SSITH_P3 Makefile, and added an undef in src_Core/Core/CoreW.bsv
2020-01-23 12:25:21 -05:00
Niraj Nayan Sharma
364b1d1cf3
For src_SSITH_P3 builds, added conditions to include/exclude
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simulation models of the integer divider
2020-01-03 16:59:34 +05:30
Darius Rad
4d1030df47
Add support for external debug module.
2019-04-09 14:08:36 -04:00
rsnikhil
47985fa93f
Updated Makefiles so in src_SSITH_P3, RTL refers to Xilinx FP RTL instead of simulation models
2019-04-04 13:10:45 -04:00
rsnikhil
113f888d37
Added support for 'debug_external_interrupt_req'
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New method 'debug_external_interrupt_req' to support emulation of a
debug module starts at P3_Core interface and is plumbed all the way in
to the CSR register MIP as interrupt [14]. The corresponding MIE[14]
is always 1, so it is never masked. Still todo: should not be masked
by MSTATUS interrupt-enables either. Also expanded
interrupt-detection logic, mcause etc. to extend up to interrupt 14.
Builds in standalone mode, runs ISA tests.
Builds in src_SSITH_P3, generating RTL.
2019-04-01 12:26:54 -04:00
