Cheri-research/Toooba
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2d05514b669be2be2b3bfa5b805cac4d0bca201b
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21 Commits

Author SHA1 Message Date
Jonathan Woodruff
3ebf537f71 Tidy up tracing options, including using RVFI when building for bluesim 
(which I'm sure we had meant to be doing?).
 2023-06-23 13:09:38 +00:00
Peter Rugg
ece8955595 Prevent reads to addresses with outstanding writes 
Untested
 2023-02-28 23:02:44 +00:00
Jonathan Woodruff
06a9221bb1 Changes for GFE hardware build with 512-bit bus. 2022-11-23 13:29:46 +00:00
Jonathan Woodruff
5f69c657c1 Use IDs in cache miss transactions to allow reordering. 2022-11-23 10:11:31 +00:00
Jonathan Woodruff
4af4b647b1 Merge branch 'CHERI' into jdw57-512axi 2022-11-14 14:51:54 +00:00
Jonathan Woodruff
066289f8aa Work in progress. 
Wd_Data is moved to 512 bits, and LLC_AXI4_Adapter is updated.
Lots of build errors now; a few have been resolved.
 2022-11-10 13:51:12 +00:00
Peter Rugg
6d4644ce73 Add tag-only state to MESI and interface with tagOnlyReq of tag controller 2022-03-31 02:07:01 +01:00
Alexandre Joannou
98a9c076cd Update BlueStuff API and Bump BlueStuff and TagController 2020-12-01 14:22:12 +00:00
Jessica Clarke
e9d212fcbc LLC_AXI4_Adapter.bsv: Make more obviously correct 
Previously we were relying on the beat count registers being exactly the
right number of bits such that we'd overflow from 7 back to 0 after the
final flit. This change aligns the LLC adapter with the MMIO adapter,
which already does things in a safer way. We can also just look at rlast
for read respones rather than a full 3-bit comparison (the MMIO adapter
also makes this micro-optimisation).
 2020-07-06 19:01:56 +01:00
Peter Rugg
c406d357c9 Add CHERI+RVFI_DII grant codes and copyrights 2020-07-06 17:39:25 +01:00
jon
86e143a9f7 Changes that are much more likely to work for uncached memory accesses, 
up to 128-bits.  I'm getting a lockup in simulation that I haven't
resolved yet, but the request looks ok.
 2020-06-24 19:45:34 +01:00
jon
078d39b9df Enable write bursts in LLC AXI4 adapter. 2020-06-02 09:40:37 +01:00
jon
ffeed959a3 Believed-to-be-working attaching of tags to write bursts in the AXI4 LLC 
wrapper.
 2020-05-28 18:21:03 +01:00
Alexandre Joannou
b70498e00a Try new types to hold capabilities 2020-04-30 14:07:37 +01:00
Alexandre Joannou
b5b2b4fe5c Port AXI4 changes from Flute 2020-03-27 16:45:26 +00:00
Jonathan Woodruff
2aa902f61a Change tabs to 8 spaces, this time being careful to do this only in BSV files. 2020-03-23 14:44:39 +00:00
Jonathan Woodruff
a6e5a7bff0 Revert "Fix whitespace in src_Core directory." 
This reverts commit a137a6ede7.
 2020-03-23 14:40:02 +00:00
Jonathan Woodruff
a137a6ede7 Fix whitespace in src_Core directory. 
Replace all tabs with 8 spaces.
 2020-03-23 14:28:00 +00:00
rsnikhil
83829590dd Fixed up logic for "Non-Debug-Module reset" request/response from the Debug Module 
Now able to run multiple ISA tests in a single simulation run
connected to remote debugger DSharp, using either hart_reset or
ndm_reset between tests to bring the system back into reset state.
All Debug Module commands working:
 - dm_reset, hart_reset, ndm_reset
 - break    (set breakpoint)
 - step
 - continue (until breakpoint of 'halt' command)
 - halt
 - read/write GPR, FPR, CSR, memory
 - elf_load
 2020-02-04 16:02:53 -05:00
rsnikhil
9f94c9176e Added verbosity guards around $displays to dial down log verbosity 
To get the instruction trace back, set verbosity to 1 in CommitStage.bsv.
Regressions: RV64ADFIMSU_Tooba_verilator: 199/227 PASS (1 test hangs)
 2019-04-01 20:35:52 -04:00
rsnikhil
ee24a93944 Initial load of files 2019-03-26 14:49:40 -04:00