6 Commits

Author	SHA1	Message	Date
rsnikhil	40b55d2c32	Fixed a Tandem-Verification issue (report MIP change due to interrupts). ... CSR MIP can change due to external/timer interrupts. These non-instruction-related changes were not being reported to the Tandem Verifier.	2020-03-03 18:34:00 -05:00
rsnikhil	8434df2dac	Fixes for Tandem Verification for store-values, CSR values on traps, etc. (detail below) ... src_Core/CPU/CsrFile.bsv Various fixes for WARL'd values of mstatus and sstatus, medeleg, Added tval field in Trap_Updates returned by csrf.trap src_Core/Core/Trace_Data2.bsv Added fields for store_data and store_data_BE src_Core/Core/Trace_Data2_to_Trace_Data.bsv Added treatment of store_data and store_data_BE Fixed bug in next_pc for mkTrace_RET src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv Fixed Trace_Data2 struct to TV for pc in case of xRET, and tval in case of trap src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv Added store_data and store_data_BE in calls to rob_setExecuted_doFinishMem src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv Added store_data and store_data_BE in methods rob_setExecuted_doFinishMem	2020-02-12 19:43:04 -05:00
rsnikhil	db114186af	More progress towards Tandem Verification trace generation (detail below) ... Now handling all Alu and Fpu pipeline outputs, traps and xRets. Still todo: (1) Mem pipeline outputs (Ld, Lr/Sc, Amo outputs to dest reg) (2) For CSRRx, currently reporting WARL pre-write updates; needs to be WARL'd update.	2020-02-10 15:08:08 -05:00
rsnikhil	c0ae2776e8	Further additions to Tandem Verification trace info. ... Rd value (destination register) of Integer ops supported Trap updates (priv and CSR updates) supported. Still pending: Memory ops Rd value, Fpu Rd value	2020-02-07 23:10:53 -05:00
rsnikhil	af0b1ef415	Incremental additions to Tandem Verification trace gen	2020-02-06 20:46:26 -05:00
rsnikhil	6078b7ce19	Removed EXTERNAL_DEBUG_MODULE stuff from CoreW.bsv; added Tandem Verif control flow	2020-01-29 13:19:31 -05:00