Commit Graph

15 Commits

Author SHA1 Message Date
rsnikhil
fa5e141550 Fixed resume-after-break problem (details below).
When controlled from a debugger (build with INCLUDE_GDB_CONTROL macro);
when stopped due a EBREAK instruction; on a 'resume' command ('continue' in GDB),
was getting stuck.  This is now working.
At this point, all debugger functionality (almost: see below) is working:
   halt, step, breakpoints, resume, read/write gpr/fpr/csr, read/write memory.
Still todo: "NDM reset" (non-debug module reset).
2020-01-17 20:08:04 -05:00
rsnikhil
977e3c92cd Fixed some ifdef INCLUDE_GDB_CONTROL issues. Passing all 229 ISA tests. 2020-01-16 16:04:32 -05:00
rsnikhil
56698d469e Integration of Debug_Module basically complete (except resume-after-break, details follow)
Stop, set breakpoint: working, stopping successfully.
Step: working: stops after a step.
Continue (resume) working after Stop and Step, but not after stop by breakpoint (needs debugging)
Read/Write GPRs, FPRs, CSRs, memory working.
2020-01-16 14:36:19 -05:00
rsnikhil
16cb92e2c1 Register reads now working. All functionality is in; need testing, cleanup, merge into master. 2020-01-15 15:54:50 -05:00
rsnikhil
2e909a90a9 Work-in-progress integrating Debug Module. Now able to load ELF file from debugger and execute it 2020-01-14 23:29:32 -05:00
rsnikhil
2807edf1b2 Work-in-progress on integrating Debug Module 2020-01-13 21:22:54 -05:00
rsnikhil
dcfb285c29 Work-in-progress. Now able to single-step from debugger. 2020-01-13 15:34:27 -05:00
rsnikhil
27c3c7cb4d Work in progress on Debug Module integration. Got further on start/step/halt 2020-01-12 22:25:14 -05:00
rsnikhil
cd779e1cbe Work in progress: updates to handle stop/step/run from Debug Module 2020-01-08 20:17:50 -05:00
James Clarke
a0fd5a8f37 Print cycle counter like Piccolo/Flute on write to to_host 2019-11-02 20:37:34 +00:00
rsnikhil
666dd2ad92 Small tweak to remove unnecessary explicit boot rom addrs (subsumed by IO) 2019-04-22 15:12:30 -04:00
Darius Rad
4d1030df47 Add support for external debug module. 2019-04-09 14:08:36 -04:00
rsnikhil
4e305ac98d Updated so SoC addrs are taken from SoC_Map.bsv 2019-04-01 14:34:49 -04:00
rsnikhil
113f888d37 Added support for 'debug_external_interrupt_req'
New method 'debug_external_interrupt_req' to support emulation of a
debug module starts at P3_Core interface and is plumbed all the way in
to the CSR register MIP as interrupt [14].  The corresponding MIE[14]
is always 1, so it is never masked. Still todo: should not be masked
by MSTATUS interrupt-enables either.  Also expanded
interrupt-detection logic, mcause etc. to extend up to interrupt 14.

Builds in standalone mode, runs ISA tests.

Builds in src_SSITH_P3, generating RTL.
2019-04-01 12:26:54 -04:00
rsnikhil
ee24a93944 Initial load of files 2019-03-26 14:49:40 -04:00