removed debug prints

.gitignore

@@ -7,6 +7,7 @@ build_dir
 obj_dir
 elf_to_hex
 Mem.hex
+exe*
 *.log
 Tests/Logs
 *_edited.v
@@ -22,4 +23,3 @@ src_SSITH_P3/Verilog_RTL_sim
 **/TagTableStructure.bsv
 **/GenerateHPMVector.bsv
 **/StatCounters.bsv
-test.txt

Tests/elf_to_hex/Makefile

@@ -0,0 +1,29 @@
+# Makefile to create an elf_to_hex executable.
+# The executable creates mem-hex files containing 32-Byte words
+
+CC = gcc
+
+# the LIBERARY path needs to be set for Apple devices, e.g.,
+# LIBRARY_PATH="$LIBRARY_PATH:$(brew --prefix)/lib"
+
+uname_S := $(shell uname -s)
+
+CFLAGS = -g  -o elf_to_hex  elf_to_hex.c -lelf
+
+ifeq ($(uname_S), Darwin)
+    CC = clang++
+    APPLE_FLAGS = -L /opt/homebrew/lib -I /opt/homebrew/include/libelf -I /opt/homebrew/include
+endif
+
+elf_to_hex: elf_to_hex.c
+	$(CC) $(CFLAGS) $(APPLE_FLAGS)
+
+# ================================================================
+
+.PHONY: clean
+clean:
+	rm  -f  *~
+
+.PHONY: full_clean
+full_clean:
+	rm  -f  *~  elf_to_hex

Tests/elf_to_hex/README.txt

@@ -0,0 +1,12 @@
+Copyright (c) 2018 Bluespec, Inc. All Rights Reserved
+
+This standalone C program takes two command-line arguments, and ELF
+filename and a Mem Hex filename.  It reads the ELF file and writes out
+the Mem Hex file.
+
+It assumes a memory that is:
+  - 16 MiB or 256 MiB (see C file)
+  - Each word is 32 bytes (256 bits)
+  - It starts at byte address 0x_8000_0000
+
+All of these can be changed by editing the C file.

Tests/elf_to_hex/elf_to_hex.c

@@ -0,0 +1,382 @@
+// Copyright (c) 2013-2018 Bluespec, Inc. All Rights Reserved
+
+// This program reads an ELF file and outputs a Verilog hex memory
+// image file (suitable for reading using $readmemh).
+
+// Modifications for CHERI as well as compiling on APPLE devices:
+
+	/*-
+	 * Copyright (c) 2022 Jonathan Woodruff
+	 * Copyright (c) 2022 Franz Fuchs
+	 * All rights reserved.
+	 *
+	 * This software was developed by the University of  Cambridge
+	 * Department of Computer Science and Technology under the
+	 * SIPP (Secure IoT Processor Platform with Remote Attestation)
+	 * project funded by EPSRC: EP/S030868/1
+	 *
+	 * @BERI_LICENSE_HEADER_START@
+	 *
+	 * Licensed to BERI Open Systems C.I.C. (BERI) under one or more contributor
+	 * license agreements.  See the NOTICE file distributed with this work for
+	 * additional information regarding copyright ownership.  BERI licenses this
+	 * file to you under the BERI Hardware-Software License, Version 1.0 (the
+	 * "License"); you may not use this file except in compliance with the
+	 * License.  You may obtain a copy of the License at:
+	 *
+	 *   http://www.beri-open-systems.org/legal/license-1-0.txt
+	 *
+	 * Unless required by applicable law or agreed to in writing, Work distributed
+	 * under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+	 * CONDITIONS OF ANY KIND, either express or implied.  See the License for the
+	 * specific language governing permissions and limitations under the License.
+	 *
+	 * @BERI_LICENSE_HEADER_END@
+	 */
+
+// ================================================================
+// Standard C includes
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <inttypes.h>
+#include <string.h>
+#include <fcntl.h>
+#include <gelf.h>
+
+#ifdef __APPLE__
+#include <vector>
+#endif
+
+// ================================================================
+// Memory buffer into which we load the ELF file before
+// writing it back out to the output file.
+
+// 1 Gigabyte size
+// #define MAX_MEM_SIZE (((uint64_t) 0x400) * ((uint64_t) 0x400) * ((uint64_t) 0x400))
+#define MAX_MEM_SIZE ((uint64_t) 0x90000000)
+
+#define BASE_ADDR_B  0x80000000lu
+
+// For 16 MB memory at 0x_8000_0000
+#define MIN_MEM_ADDR_16MB  BASE_ADDR_B
+#define MAX_MEM_ADDR_16MB  (BASE_ADDR_B + 0x1000000lu)
+
+// For 1 GB memory at 0x_8000_0000
+#define MIN_MEM_ADDR_1GB  BASE_ADDR_B
+#define MAX_MEM_ADDR_1GB  (BASE_ADDR_B + 0x40000000lu)
+
+uint8_t *mem_buf;
+
+// Features of the ELF binary
+int       bitwidth;
+uint64_t  min_addr;
+uint64_t  max_addr;
+
+uint64_t  pc_start;       // Addr of label  '_start'
+uint64_t  pc_exit;        // Addr of label  'exit'
+uint64_t  tohost_addr;    // Addr of label  'tohost'
+
+// ================================================================
+// Load an ELF file.
+
+void c_mem_load_elf (char *elf_filename,
+		     const char *start_symbol,
+		     const char *exit_symbol,
+		     const char *tohost_symbol)
+{
+    int fd;
+    // int n_initialized = 0;
+    Elf *e;
+
+    // Default start, exit and tohost symbols
+    if (start_symbol == NULL)
+	start_symbol = "_start";
+    if (exit_symbol == NULL)
+	exit_symbol = "exit";
+    if (tohost_symbol == NULL)
+	tohost_symbol = "tohost";
+    
+    // Verify the elf library version
+    if (elf_version (EV_CURRENT) == EV_NONE) {
+        fprintf (stderr, "ERROR: c_mem_load_elf: Failed to initialize the libelfg library!\n");
+	exit (1);
+    }
+
+    // Open the file for reading
+    fd = open (elf_filename, O_RDONLY, 0);
+    if (fd < 0) {
+        fprintf (stderr, "ERROR: c_mem_load_elf: could not open elf input file: %s\n", elf_filename);
+	exit (1);
+    }
+
+    // Initialize the Elf pointer with the open file
+    e = elf_begin (fd, ELF_C_READ, NULL);
+    if (e == NULL) {
+        fprintf (stderr, "ERROR: c_mem_load_elf: elf_begin() initialization failed!\n");
+	exit (1);
+    }
+
+    // Verify that the file is an ELF file
+    if (elf_kind (e) != ELF_K_ELF) {
+        elf_end (e);
+        fprintf (stderr, "ERROR: c_mem_load_elf: specified file '%s' is not an ELF file!\n", elf_filename);
+	exit (1);
+    }
+
+    // Get the ELF header
+    GElf_Ehdr ehdr;
+    if (gelf_getehdr (e, & ehdr) == NULL) {
+        elf_end (e);
+        fprintf (stderr, "ERROR: c_mem_load_elf: get_getehdr() failed: %s\n", elf_errmsg(-1));
+	exit (1);
+    }
+
+    // Is this a 32b or 64 ELF?
+    if (gelf_getclass (e) == ELFCLASS32) {
+	fprintf (stdout, "c_mem_load_elf: %s is a 32-bit ELF file\n", elf_filename);
+	bitwidth = 32;
+    }
+    else if (gelf_getclass (e) == ELFCLASS64) {
+	fprintf (stdout, "c_mem_load_elf: %s is a 64-bit ELF file\n", elf_filename);
+	bitwidth = 64;
+    }
+    else {
+        fprintf (stderr, "ERROR: c_mem_load_elf: ELF file '%s' is not 32b or 64b\n", elf_filename);
+	elf_end (e);
+	exit (1);
+    }
+
+    // Verify we are dealing with a RISC-V ELF
+    if (ehdr.e_machine != 243) { // EM_RISCV is not defined, but this returns 243 when used with a valid elf file.
+        elf_end (e);
+        fprintf (stderr, "ERROR: c_mem_load_elf: %s is not a RISC-V ELF file\n", elf_filename);
+	exit (1);
+    }
+
+    // Verify we are dealing with a little endian ELF
+    if (ehdr.e_ident[EI_DATA] != ELFDATA2LSB) {
+        elf_end (e);
+        fprintf (stderr,
+		 "ERROR: c_mem_load_elf: %s is a big-endian 64-bit RISC-V executable which is not supported\n",
+		 elf_filename);
+	exit (1);
+    }
+
+    // Grab the string section index
+    size_t shstrndx;
+    shstrndx = ehdr.e_shstrndx;
+
+    // Iterate through each of the sections looking for code that should be loaded
+    Elf_Scn  *scn   = 0;
+    GElf_Shdr shdr;
+
+    min_addr    = 0xFFFFFFFFFFFFFFFFllu;
+    max_addr    = 0x0000000000000000llu;
+    pc_start    = 0xFFFFFFFFFFFFFFFFllu;
+    pc_exit     = 0xFFFFFFFFFFFFFFFFllu;
+    tohost_addr = 0xFFFFFFFFFFFFFFFFllu;
+
+    while ((scn = elf_nextscn (e,scn)) != NULL) {
+        // get the header information for this section
+        gelf_getshdr (scn, & shdr);
+
+	char *sec_name = elf_strptr (e, shstrndx, shdr.sh_name);
+	fprintf (stdout, "Section %-16s: ", sec_name);
+
+	Elf_Data *data = 0;
+	// If we find a code/data section, load it into the model
+	if (   ((shdr.sh_type == SHT_PROGBITS)
+		|| (shdr.sh_type == SHT_NOBITS)
+		|| (shdr.sh_type == SHT_INIT_ARRAY)
+		|| (shdr.sh_type == SHT_FINI_ARRAY))
+	    && ((shdr.sh_flags & SHF_WRITE)
+		|| (shdr.sh_flags & SHF_ALLOC)
+		|| (shdr.sh_flags & SHF_EXECINSTR))) {
+	    data = elf_getdata (scn, data);
+
+	    // n_initialized += data->d_size;
+	    if (shdr.sh_addr < min_addr)
+		min_addr = shdr.sh_addr;
+	    if (max_addr < (shdr.sh_addr + data->d_size - 1))   // shdr.sh_size + 4))
+		max_addr = shdr.sh_addr + data->d_size - 1;    // shdr.sh_size + 4;
+
+	    if (max_addr >= MAX_MEM_SIZE) {
+		fprintf (stdout, "INTERNAL ERROR: max_addr (0x%0" PRIx64 ") > buffer size (0x%0" PRIx64 ")\n",
+			 max_addr, MAX_MEM_SIZE);
+		fprintf (stdout, "    Please increase the #define in this program, recompile, and run again\n");
+		fprintf (stdout, "    Abandoning this run\n");
+		exit (1);
+	    }
+
+	    if (shdr.sh_type != SHT_NOBITS && shdr.sh_addr!=0) {
+		memcpy (& (mem_buf [shdr.sh_addr-MIN_MEM_ADDR_1GB]), data->d_buf, data->d_size);
+	    }
+	    fprintf (stdout, "addr %16" PRIx64 " to addr %16" PRIx64 "; size 0x%8lx (= %0ld) bytes\n",
+		     shdr.sh_addr, shdr.sh_addr + data->d_size, data->d_size, data->d_size);
+
+	}
+
+	// If we find the symbol table, search for symbols of interest
+	else if (shdr.sh_type == SHT_SYMTAB) {
+	    fprintf (stdout, "Searching for addresses of '%s', '%s' and '%s' symbols\n",
+		     start_symbol, exit_symbol, tohost_symbol);
+
+ 	    // Get the section data
+	    data = elf_getdata (scn, data);
+
+	    // Get the number of symbols in this section
+	    int symbols = shdr.sh_size / shdr.sh_entsize;
+
+	    // search for the uart_default symbols we need to potentially modify.
+	    GElf_Sym sym;
+	    int i;
+	    for (i = 0; i < symbols; ++i) {
+	        // get the symbol data
+	        gelf_getsym (data, i, &sym);
+
+		// get the name of the symbol
+		char *name = elf_strptr (e, shdr.sh_link, sym.st_name);
+
+		// Look for, and remember PC of the start symbol
+		if (strcmp (name, start_symbol) == 0) {
+		    pc_start = sym.st_value;
+		}
+		// Look for, and remember PC of the exit symbol
+		else if (strcmp (name, exit_symbol) == 0) {
+		    pc_exit = sym.st_value;
+		}
+		// Look for, and remember addr of 'tohost' symbol
+		else if (strcmp (name, tohost_symbol) == 0) {
+		    tohost_addr = sym.st_value;
+		}
+	    }
+
+	    FILE *fp_symbol_table = fopen ("symbol_table.txt", "w");
+	    if (fp_symbol_table != NULL) {
+		fprintf (stdout, "Writing symbols to:    symbol_table.txt\n");
+		if (pc_start == -1)
+		    fprintf (stdout, "    No '_start' label found\n");
+		else
+		    fprintf (fp_symbol_table, "_start    0x%0" PRIx64 "\n", pc_start);
+
+		if (pc_exit == -1)
+		    fprintf (stdout, "    No 'exit' label found\n");
+		else
+		    fprintf (fp_symbol_table, "exit      0x%0" PRIx64 "\n", pc_exit);
+
+		if (tohost_addr == -1)
+		    fprintf (stdout, "    No 'tohost' symbol found\n");
+		else
+		    fprintf (fp_symbol_table, "tohost    0x%0" PRIx64 "\n", tohost_addr);
+
+		fclose (fp_symbol_table);
+	    }
+	}
+	else {
+	    fprintf (stdout, "Ignored\n");
+	}
+    }
+
+    elf_end (e);
+
+    fprintf (stdout, "Min addr:            %16" PRIx64 " (hex)\n", min_addr);
+    fprintf (stdout, "Max addr:            %16" PRIx64 " (hex)\n", max_addr);
+}
+
+// ================================================================
+
+// Write out from word containing addr1 to word containing addr2
+void write_mem_hex_file (FILE *fp, uint64_t addr1, uint64_t addr2)
+{
+    const uint64_t bits_per_raw_mem_word   = 256;
+    uint64_t bytes_per_raw_mem_word  = bits_per_raw_mem_word / 8;    // 32
+    uint64_t raw_mem_word_align_mask = (~ ((uint64_t) (bytes_per_raw_mem_word - 1)));
+
+    fprintf (stdout, "Subtracting 0x%08" PRIx64 " base from addresses\n", BASE_ADDR_B);
+
+    // Align the start and end addrs to raw mem words
+    uint64_t a1 = (addr1 & raw_mem_word_align_mask);
+    uint64_t a2 = ((addr2 + bytes_per_raw_mem_word - 1) & raw_mem_word_align_mask);
+
+    fprintf (fp, "@%07" PRIx64 "    // raw_mem addr;  byte addr: %08" PRIx64 "\n",
+	     ((a1 - BASE_ADDR_B) / bytes_per_raw_mem_word),
+	     a1 - BASE_ADDR_B);
+	     
+    uint64_t addr;
+    for (addr = a1; addr < a2; addr += bytes_per_raw_mem_word) {
+	for (int j = (bytes_per_raw_mem_word - 1); j >= 0; j--)
+	    fprintf (fp, "%02x", mem_buf [addr+j-MIN_MEM_ADDR_1GB]);
+	fprintf (fp, "    // raw_mem addr %08" PRIx64 ";  byte addr %08" PRIx64 "\n",
+		 ((addr - BASE_ADDR_B) / bytes_per_raw_mem_word),
+		 (addr  - BASE_ADDR_B));
+    }
+
+    // Write last word, if necessary, to avoid warnings about missing locations
+    if (addr < (MAX_MEM_ADDR_1GB - bytes_per_raw_mem_word)) {
+	addr = MAX_MEM_ADDR_1GB - bytes_per_raw_mem_word;
+	fprintf (fp, "@%07" PRIx64 "    // last raw_mem addr;  byte addr: %08" PRIx64 "\n",
+		 ((addr - BASE_ADDR_B) / bytes_per_raw_mem_word),
+		 addr - BASE_ADDR_B);
+	for (int j = (bytes_per_raw_mem_word - 1); j >= 0; j--)
+	    fprintf (fp, "%02x", 0);
+	fprintf (fp, "    // raw_mem addr %08" PRIx64 ";  byte addr %08" PRIx64 "\n",
+		 ((addr - BASE_ADDR_B) / bytes_per_raw_mem_word),
+		 (addr  - BASE_ADDR_B));
+    }
+}
+
+// ================================================================
+
+void print_usage (FILE *fp, int argc, char *argv [])
+{
+    fprintf (fp, "Usage:\n");
+    fprintf (fp, "    %s  --help\n", argv [0]);
+    fprintf (fp, "    %s  <ELF filename>  <mem hex filename>\n", argv [0]);
+    fprintf (fp, "Reads ELF file and writes a Verilog Hex Memory image file\n");
+    fprintf (fp, "ELF file should have addresses within this range:\n");
+    fprintf (fp, "<  Max: 0x%8" PRIx64 "\n", MAX_MEM_ADDR_1GB);
+    fprintf (fp, ">= Min: 0x%8" PRIx64 "\n", MIN_MEM_ADDR_1GB);
+}
+
+// ================================================================
+
+int main (int argc, char *argv [])
+{
+    if ((argc == 2) && (strcmp (argv [1], "--help") == 0)) {
+	print_usage (stdout, argc, argv);
+	return 0;
+    }
+    else if (argc != 3) {
+	print_usage (stderr, argc, argv);
+	return 1;
+    }
+
+    // Zero out the memory buffer before loading the ELF file
+    mem_buf = (uint8_t *)(calloc(MAX_MEM_SIZE, sizeof(uint8_t)));
+    if (mem_buf == NULL) {
+	fprintf (stderr, "ERROR: unable to allocate %lxMB for mem_buf\n", MAX_MEM_SIZE / 1024 / 1024);
+	return 1;
+    }
+
+    c_mem_load_elf (argv [1], "_start", "exit", "tohost");
+
+    if ((min_addr < BASE_ADDR_B) || (MAX_MEM_ADDR_1GB <= max_addr)) {
+	print_usage (stderr, argc, argv);
+	exit (1);
+    }
+
+    FILE *fp_out = fopen (argv [2], "w");
+    if (fp_out == NULL) {
+	fprintf (stderr, "ERROR: unable to open file '%s' for output\n", argv [2]);
+	return 1;
+    }
+
+    fprintf (stdout, "Writing mem hex to file '%s'\n", argv [2]);
+    write_mem_hex_file (fp_out, BASE_ADDR_B, max_addr);
+    // write_mem_hex_file (fp_out, BASE_ADDR_B, MAX_MEM_ADDR_1GB);
+
+    free(mem_buf);
+    fclose (fp_out);
+}

Tests/isa/Baremetal-C-programs/entry.S

@@ -1,164 +0,0 @@
-#include "riscv_test.h"
-
-#if __riscv_xlen == 64
-# define STORE    sd
-# define LOAD     ld
-# define REGBYTES 8
-#else
-# define STORE    sw
-# define LOAD     lw
-# define REGBYTES 4
-#endif
-
-#define STACK_TOP (_end + RISCV_PGSIZE * 4)
-
-  .section ".text.init","ax",@progbits
-  .globl _start
-  .align 2
-_start:
-  j handle_reset
-
-  /* NMI vector */
-  .align 2
-nmi_vector:
-  j wtf
-
-  .align 2
-trap_vector:
-  j wtf
-
-handle_reset:
-  li x1, 0
-  li x2, 0
-  li x3, 0
-  li x4, 0
-  li x5, 0
-  li x6, 0
-  li x7, 0
-  li x8, 0
-  li x9, 0
-  li x10, 0
-  li x11, 0
-  li x12, 0
-  li x13, 0
-  li x14, 0
-  li x15, 0
-  li x16, 0
-  li x17, 0
-  li x18, 0
-  li x19, 0
-  li x20, 0
-  li x21, 0
-  li x22, 0
-  li x23, 0
-  li x24, 0
-  li x25, 0
-  li x26, 0
-  li x27, 0
-  li x28, 0
-  li x29, 0
-  li x30, 0
-  li x31, 0
-
-  INIT_RNMI
-
-  la t0, trap_vector
-  csrw mtvec, t0
-  la sp, STACK_TOP - SIZEOF_TRAPFRAME_T
-  csrr t0, mhartid
-  slli t0, t0, 12
-  add sp, sp, t0
-  csrw mscratch, sp
-  call extra_boot
-  la a0, userstart
-  j vm_boot
-
-  .globl  pop_tf
-pop_tf:
-  LOAD  t0,33*REGBYTES(a0)
-  csrw  sepc,t0
-  LOAD  x1,1*REGBYTES(a0)
-  LOAD  x2,2*REGBYTES(a0)
-  LOAD  x3,3*REGBYTES(a0)
-  LOAD  x4,4*REGBYTES(a0)
-  LOAD  x5,5*REGBYTES(a0)
-  LOAD  x6,6*REGBYTES(a0)
-  LOAD  x7,7*REGBYTES(a0)
-  LOAD  x8,8*REGBYTES(a0)
-  LOAD  x9,9*REGBYTES(a0)
-  LOAD  x11,11*REGBYTES(a0)
-  LOAD  x12,12*REGBYTES(a0)
-  LOAD  x13,13*REGBYTES(a0)
-  LOAD  x14,14*REGBYTES(a0)
-  LOAD  x15,15*REGBYTES(a0)
-  LOAD  x16,16*REGBYTES(a0)
-  LOAD  x17,17*REGBYTES(a0)
-  LOAD  x18,18*REGBYTES(a0)
-  LOAD  x19,19*REGBYTES(a0)
-  LOAD  x20,20*REGBYTES(a0)
-  LOAD  x21,21*REGBYTES(a0)
-  LOAD  x22,22*REGBYTES(a0)
-  LOAD  x23,23*REGBYTES(a0)
-  LOAD  x24,24*REGBYTES(a0)
-  LOAD  x25,25*REGBYTES(a0)
-  LOAD  x26,26*REGBYTES(a0)
-  LOAD  x27,27*REGBYTES(a0)
-  LOAD  x28,28*REGBYTES(a0)
-  LOAD  x29,29*REGBYTES(a0)
-  LOAD  x30,30*REGBYTES(a0)
-  LOAD  x31,31*REGBYTES(a0)
-  LOAD  a0,10*REGBYTES(a0)
-  sret
-
-  .global  trap_entry
-  .align 2
-trap_entry:
-  csrrw sp, sscratch, sp
-
-  # save gprs
-  STORE  x1,1*REGBYTES(sp)
-  STORE  x3,3*REGBYTES(sp)
-  STORE  x4,4*REGBYTES(sp)
-  STORE  x5,5*REGBYTES(sp)
-  STORE  x6,6*REGBYTES(sp)
-  STORE  x7,7*REGBYTES(sp)
-  STORE  x8,8*REGBYTES(sp)
-  STORE  x9,9*REGBYTES(sp)
-  STORE  x10,10*REGBYTES(sp)
-  STORE  x11,11*REGBYTES(sp)
-  STORE  x12,12*REGBYTES(sp)
-  STORE  x13,13*REGBYTES(sp)
-  STORE  x14,14*REGBYTES(sp)
-  STORE  x15,15*REGBYTES(sp)
-  STORE  x16,16*REGBYTES(sp)
-  STORE  x17,17*REGBYTES(sp)
-  STORE  x18,18*REGBYTES(sp)
-  STORE  x19,19*REGBYTES(sp)
-  STORE  x20,20*REGBYTES(sp)
-  STORE  x21,21*REGBYTES(sp)
-  STORE  x22,22*REGBYTES(sp)
-  STORE  x23,23*REGBYTES(sp)
-  STORE  x24,24*REGBYTES(sp)
-  STORE  x25,25*REGBYTES(sp)
-  STORE  x26,26*REGBYTES(sp)
-  STORE  x27,27*REGBYTES(sp)
-  STORE  x28,28*REGBYTES(sp)
-  STORE  x29,29*REGBYTES(sp)
-  STORE  x30,30*REGBYTES(sp)
-  STORE  x31,31*REGBYTES(sp)
-
-  csrrw  t0,sscratch,sp
-  STORE  t0,2*REGBYTES(sp)
-
-  # get sr, epc, badvaddr, cause
-  csrr   t0,sstatus
-  STORE  t0,32*REGBYTES(sp)
-  csrr   t0,sepc
-  STORE  t0,33*REGBYTES(sp)
-  csrr   t0,stval
-  STORE  t0,34*REGBYTES(sp)
-  csrr   t0,scause
-  STORE  t0,35*REGBYTES(sp)
-
-  move  a0, sp
-  j handle_trap

Tests/isa/Baremetal-C-programs/link.ld

@@ -1,16 +0,0 @@
-OUTPUT_ARCH( "riscv" )
-ENTRY(_start)
-
-SECTIONS
-{
-  . = 0x80000000;
-  .text.init : { *(.text.init) }
-  . = ALIGN(0x1000);
-  .tohost : { *(.tohost) }
-  . = ALIGN(0x1000);
-  .text : { *(.text) }
-  . = ALIGN(0x1000);
-  .data : { *(.data) }
-  .bss : { *(.bss) }
-  _end = .;
-}

Tests/isa/Baremetal-C-programs/riscv_test.h

@@ -1,98 +0,0 @@
-// See LICENSE for license details.
-
-#ifndef _ENV_VIRTUAL_SINGLE_CORE_H
-#define _ENV_VIRTUAL_SINGLE_CORE_H
-
-#include "../p/riscv_test.h"
-
-//-----------------------------------------------------------------------
-// Begin Macro
-//-----------------------------------------------------------------------
-
-#undef RVTEST_FP_ENABLE
-#define RVTEST_FP_ENABLE fssr x0
-
-#undef RVTEST_VECTOR_ENABLE
-#define RVTEST_VECTOR_ENABLE                                            \
-  csrwi fcsr, 0;                                                        \
-  csrwi vcsr, 0;
-
-#undef RVTEST_ZVE32X_ENABLE
-#define RVTEST_ZVE32X_ENABLE                                            \
-  csrwi vcsr, 0;
-
-#undef RVTEST_CODE_BEGIN
-#define RVTEST_CODE_BEGIN                                               \
-        .text;                                                          \
-        .global extra_boot;                                             \
-extra_boot:                                                             \
-        EXTRA_INIT                                                      \
-        ret;                                                            \
-.global trap_filter;                                                    \
-trap_filter:                                                            \
-        FILTER_TRAP                                                     \
-        li a0, 0;                                                       \
-        ret;                                                            \
-.global pf_filter;                                                      \
-pf_filter:                                                              \
-        FILTER_PAGE_FAULT                                               \
-        li a0, 0;                                                       \
-        ret;                                                            \
-        .global userstart;                                              \
-userstart:                                                              \
-        init
-
-//-----------------------------------------------------------------------
-// Pass/Fail Macro
-//-----------------------------------------------------------------------
-
-#undef RVTEST_PASS
-#define RVTEST_PASS li a0, 1; scall
-
-#undef RVTEST_FAIL
-#define RVTEST_FAIL sll a0, TESTNUM, 1; 1:beqz a0, 1b; or a0, a0, 1; scall;
-
-//-----------------------------------------------------------------------
-// Data Section Macro
-//-----------------------------------------------------------------------
-
-#undef RVTEST_DATA_END
-#define RVTEST_DATA_END
-
-//-----------------------------------------------------------------------
-// Supervisor mode definitions and macros
-//-----------------------------------------------------------------------
-
-#ifndef LFSR_BITS
-#define LFSR_BITS 6
-#endif
-
-#define MAX_TEST_PAGES ((1 << LFSR_BITS)-1) // this must be the period of the LFSR below
-#define LFSR_NEXT(x) (((((x)^((x)>>1)) & 1) << (LFSR_BITS-1)) | ((x) >> 1))
-
-#define PGSHIFT 12
-#define PGSIZE (1UL << PGSHIFT)
-
-#define SIZEOF_TRAPFRAME_T ((__riscv_xlen / 8) * 36)
-
-#ifndef __ASSEMBLER__
-
-typedef unsigned long pte_t;
-#define LEVELS (sizeof(pte_t) == sizeof(uint64_t) ? 3 : 2)
-#define PTIDXBITS (PGSHIFT - (sizeof(pte_t) == 8 ? 3 : 2))
-#define VPN_BITS (PTIDXBITS * LEVELS)
-#define VA_BITS (VPN_BITS + PGSHIFT)
-#define PTES_PER_PT (1UL << RISCV_PGLEVEL_BITS)
-#define MEGAPAGE_SIZE (PTES_PER_PT * PGSIZE)
-
-typedef struct
-{
-  long gpr[32];
-  long sr;
-  long epc;
-  long badvaddr;
-  long cause;
-} trapframe_t;
-#endif
-
-#endif

Tests/isa/Baremetal-C-programs/riscv_test_p.h

@@ -1,295 +0,0 @@
-// See LICENSE for license details.
-
-#ifndef _ENV_PHYSICAL_SINGLE_CORE_H
-#define _ENV_PHYSICAL_SINGLE_CORE_H
-
-#include "../encoding.h"
-
-//-----------------------------------------------------------------------
-// Begin Macro
-//-----------------------------------------------------------------------
-
-#define RVTEST_RV64U                                                    \
-  .macro init;                                                          \
-  .endm
-
-#define RVTEST_RV64UF                                                   \
-  .macro init;                                                          \
-  RVTEST_FP_ENABLE;                                                     \
-  .endm
-
-#define RVTEST_RV64UV                                                   \
-  .macro init;                                                          \
-  RVTEST_VECTOR_ENABLE;                                                 \
-  .endm
-
-#define RVTEST_RV64UVX                                                  \
-  .macro init;                                                          \
-  RVTEST_ZVE32X_ENABLE;                                                 \
-  .endm
-
-#define RVTEST_RV32U                                                    \
-  .macro init;                                                          \
-  .endm
-
-#define RVTEST_RV32UF                                                   \
-  .macro init;                                                          \
-  RVTEST_FP_ENABLE;                                                     \
-  .endm
-
-#define RVTEST_RV32UV                                                   \
-  .macro init;                                                          \
-  RVTEST_VECTOR_ENABLE;                                                 \
-  .endm
-
-#define RVTEST_RV32UVX                                                  \
-  .macro init;                                                          \
-  RVTEST_ZVE32X_ENABLE;                                                 \
-  .endm
-
-#define RVTEST_RV64M                                                    \
-  .macro init;                                                          \
-  RVTEST_ENABLE_MACHINE;                                                \
-  .endm
-
-#define RVTEST_RV64S                                                    \
-  .macro init;                                                          \
-  RVTEST_ENABLE_SUPERVISOR;                                             \
-  .endm
-
-#define RVTEST_RV32M                                                    \
-  .macro init;                                                          \
-  RVTEST_ENABLE_MACHINE;                                                \
-  .endm
-
-#define RVTEST_RV32S                                                    \
-  .macro init;                                                          \
-  RVTEST_ENABLE_SUPERVISOR;                                             \
-  .endm
-
-#if __riscv_xlen == 64
-# define CHECK_XLEN li a0, 1; slli a0, a0, 31; bgez a0, 1f; RVTEST_PASS; 1:
-#else
-# define CHECK_XLEN li a0, 1; slli a0, a0, 31; bltz a0, 1f; RVTEST_PASS; 1:
-#endif
-
-#define INIT_XREG                                                       \
-  li x1, 0;                                                             \
-  li x2, 0;                                                             \
-  li x3, 0;                                                             \
-  li x4, 0;                                                             \
-  li x5, 0;                                                             \
-  li x6, 0;                                                             \
-  li x7, 0;                                                             \
-  li x8, 0;                                                             \
-  li x9, 0;                                                             \
-  li x10, 0;                                                            \
-  li x11, 0;                                                            \
-  li x12, 0;                                                            \
-  li x13, 0;                                                            \
-  li x14, 0;                                                            \
-  li x15, 0;                                                            \
-  li x16, 0;                                                            \
-  li x17, 0;                                                            \
-  li x18, 0;                                                            \
-  li x19, 0;                                                            \
-  li x20, 0;                                                            \
-  li x21, 0;                                                            \
-  li x22, 0;                                                            \
-  li x23, 0;                                                            \
-  li x24, 0;                                                            \
-  li x25, 0;                                                            \
-  li x26, 0;                                                            \
-  li x27, 0;                                                            \
-  li x28, 0;                                                            \
-  li x29, 0;                                                            \
-  li x30, 0;                                                            \
-  li x31, 0;
-
-#define INIT_PMP                                                        \
-  la t0, 1f;                                                            \
-  csrw mtvec, t0;                                                       \
-  /* Set up a PMP to permit all accesses */                             \
-  li t0, (1 << (31 + (__riscv_xlen / 64) * (53 - 31))) - 1;             \
-  csrw pmpaddr0, t0;                                                    \
-  li t0, PMP_NAPOT | PMP_R | PMP_W | PMP_X;                             \
-  csrw pmpcfg0, t0;                                                     \
-  .align 2;                                                             \
-1:
-
-#define INIT_RNMI                                                       \
-  la t0, 1f;                                                            \
-  csrw mtvec, t0;                                                       \
-  csrwi CSR_MNSTATUS, MNSTATUS_NMIE;                                    \
-  .align 2;                                                             \
-1:
-
-#define INIT_SATP                                                      \
-  la t0, 1f;                                                            \
-  csrw mtvec, t0;                                                       \
-  csrwi satp, 0;                                                       \
-  .align 2;                                                             \
-1:
-
-#define DELEGATE_NO_TRAPS                                               \
-  csrwi mie, 0;                                                         \
-  la t0, 1f;                                                            \
-  csrw mtvec, t0;                                                       \
-  csrwi medeleg, 0;                                                     \
-  csrwi mideleg, 0;                                                     \
-  .align 2;                                                             \
-1:
-
-#define RVTEST_ENABLE_SUPERVISOR                                        \
-  li a0, MSTATUS_MPP & (MSTATUS_MPP >> 1);                              \
-  csrs mstatus, a0;                                                     \
-  li a0, SIP_SSIP | SIP_STIP;                                           \
-  csrs mideleg, a0;                                                     \
-
-#define RVTEST_ENABLE_MACHINE                                           \
-  li a0, MSTATUS_MPP;                                                   \
-  csrs mstatus, a0;                                                     \
-
-#define RVTEST_FP_ENABLE                                                \
-  li a0, MSTATUS_FS & (MSTATUS_FS >> 1);                                \
-  csrs mstatus, a0;                                                     \
-  csrwi fcsr, 0
-
-#define RVTEST_VECTOR_ENABLE                                            \
-  li a0, (MSTATUS_VS & (MSTATUS_VS >> 1)) |                             \
-         (MSTATUS_FS & (MSTATUS_FS >> 1));                              \
-  csrs mstatus, a0;                                                     \
-  csrwi fcsr, 0;                                                        \
-  csrwi vcsr, 0;
-
-#define RVTEST_ZVE32X_ENABLE                                            \
-  li a0, (MSTATUS_VS & (MSTATUS_VS >> 1));                              \
-  csrs mstatus, a0;                                                     \
-  csrwi vcsr, 0;
-
-#define RISCV_MULTICORE_DISABLE                                         \
-  csrr a0, mhartid;                                                     \
-  1: bnez a0, 1b
-
-#define EXTRA_TVEC_USER
-#define EXTRA_TVEC_MACHINE
-#define EXTRA_INIT
-#define EXTRA_INIT_TIMER
-#define FILTER_TRAP
-#define FILTER_PAGE_FAULT
-
-#define INTERRUPT_HANDLER j other_exception /* No interrupts should occur */
-
-#define RVTEST_CODE_BEGIN                                               \
-        .section .text.init;                                            \
-        .align  6;                                                      \
-        .weak stvec_handler;                                            \
-        .weak mtvec_handler;                                            \
-        .globl _start;                                                  \
-_start:                                                                 \
-        /* reset vector */                                              \
-        j reset_vector;                                                 \
-        .align 2;                                                       \
-trap_vector:                                                            \
-        /* test whether the test came from pass/fail */                 \
-        csrr t5, mcause;                                                \
-        li t6, CAUSE_USER_ECALL;                                        \
-        beq t5, t6, write_tohost;                                       \
-        li t6, CAUSE_SUPERVISOR_ECALL;                                  \
-        beq t5, t6, write_tohost;                                       \
-        li t6, CAUSE_MACHINE_ECALL;                                     \
-        beq t5, t6, write_tohost;                                       \
-        /* if an mtvec_handler is defined, jump to it */                \
-        la t5, mtvec_handler;                                           \
-        beqz t5, 1f;                                                    \
-        jr t5;                                                          \
-        /* was it an interrupt or an exception? */                      \
-  1:    csrr t5, mcause;                                                \
-        bgez t5, handle_exception;                                      \
-        INTERRUPT_HANDLER;                                              \
-handle_exception:                                                       \
-        /* we don't know how to handle whatever the exception was */    \
-  other_exception:                                                      \
-        /* some unhandlable exception occurred */                       \
-  1:    ori TESTNUM, TESTNUM, 1337;                                     \
-  write_tohost:                                                         \
-        sw TESTNUM, tohost, t5;                                         \
-        sw zero, tohost + 4, t5;                                        \
-        j write_tohost;                                                 \
-reset_vector:                                                           \
-        INIT_XREG;                                                      \
-        RISCV_MULTICORE_DISABLE;                                        \
-        INIT_RNMI;                                                      \
-        INIT_SATP;                                                      \
-        INIT_PMP;                                                       \
-        DELEGATE_NO_TRAPS;                                              \
-        li TESTNUM, 0;                                                  \
-        la t0, trap_vector;                                             \
-        csrw mtvec, t0;                                                 \
-        CHECK_XLEN;                                                     \
-        /* if an stvec_handler is defined, delegate exceptions to it */ \
-        la t0, stvec_handler;                                           \
-        beqz t0, 1f;                                                    \
-        csrw stvec, t0;                                                 \
-        li t0, (1 << CAUSE_LOAD_PAGE_FAULT) |                           \
-               (1 << CAUSE_STORE_PAGE_FAULT) |                          \
-               (1 << CAUSE_FETCH_PAGE_FAULT) |                          \
-               (1 << CAUSE_MISALIGNED_FETCH) |                          \
-               (1 << CAUSE_USER_ECALL) |                                \
-               (1 << CAUSE_BREAKPOINT);                                 \
-        csrw medeleg, t0;                                               \
-1:      csrwi mstatus, 0;                                               \
-        init;                                                           \
-        EXTRA_INIT;                                                     \
-        EXTRA_INIT_TIMER;                                               \
-        la t0, 1f;                                                      \
-        csrw mepc, t0;                                                  \
-        csrr a0, mhartid;                                               \
-        mret;                                                           \
-1:
-
-//-----------------------------------------------------------------------
-// End Macro
-//-----------------------------------------------------------------------
-
-#define RVTEST_CODE_END                                                 \
-        unimp
-
-//-----------------------------------------------------------------------
-// Pass/Fail Macro
-//-----------------------------------------------------------------------
-
-#define RVTEST_PASS                                                     \
-        fence;                                                          \
-        li TESTNUM, 1;                                                  \
-        li a7, 93;                                                      \
-        li a0, 0;                                                       \
-        ecall
-
-#define TESTNUM gp
-#define RVTEST_FAIL                                                     \
-        fence;                                                          \
-1:      beqz TESTNUM, 1b;                                               \
-        sll TESTNUM, TESTNUM, 1;                                        \
-        or TESTNUM, TESTNUM, 1;                                         \
-        li a7, 93;                                                      \
-        addi a0, TESTNUM, 0;                                            \
-        ecall
-
-//-----------------------------------------------------------------------
-// Data Section Macro
-//-----------------------------------------------------------------------
-
-#define EXTRA_DATA
-
-#define RVTEST_DATA_BEGIN                                               \
-        EXTRA_DATA                                                      \
-        .pushsection .tohost,"aw",@progbits;                            \
-        .align 6; .global tohost; tohost: .dword 0; .size tohost, 8;    \
-        .align 6; .global fromhost; fromhost: .dword 0; .size fromhost, 8;\
-        .popsection;                                                    \
-        .align 4; .global begin_signature; begin_signature:
-
-#define RVTEST_DATA_END .align 4; .global end_signature; end_signature:
-
-#endif

Tests/isa/Baremetal-C-programs/string.c

@@ -1,114 +0,0 @@
-#include <string.h>
-#include <stdint.h>
-#include <ctype.h>
-
-void* memcpy(void* dest, const void* src, size_t len)
-{
-  if ((((uintptr_t)dest | (uintptr_t)src | len) & (sizeof(uintptr_t)-1)) == 0) {
-    const uintptr_t* s = src;
-    uintptr_t *d = dest;
-    while (d < (uintptr_t*)(dest + len))
-      *d++ = *s++;
-  } else {
-    const char* s = src;
-    char *d = dest;
-    while (d < (char*)(dest + len))
-      *d++ = *s++;
-  }
-  return dest;
-}
-
-void* memset(void* dest, int byte, size_t len)
-{
-  if ((((uintptr_t)dest | len) & (sizeof(uintptr_t)-1)) == 0) {
-    uintptr_t word = byte & 0xFF;
-    word |= word << 8;
-    word |= word << 16;
-    word |= word << 16 << 16;
-
-    uintptr_t *d = dest;
-    while (d < (uintptr_t*)(dest + len))
-      *d++ = word;
-  } else {
-    char *d = dest;
-    while (d < (char*)(dest + len))
-      *d++ = byte;
-  }
-  return dest;
-}
-
-size_t strlen(const char *s)
-{
-  const char *p = s;
-  while (*p)
-    p++;
-  return p - s;
-}
-
-int strcmp(const char* s1, const char* s2)
-{
-  unsigned char c1, c2;
-
-  do {
-    c1 = *s1++;
-    c2 = *s2++;
-  } while (c1 != 0 && c1 == c2);
-
-  return c1 - c2;
-}
-
-int memcmp(const void* s1, const void* s2, size_t n)
-{
-  if ((((uintptr_t)s1 | (uintptr_t)s2) & (sizeof(uintptr_t)-1)) == 0) {
-    const uintptr_t* u1 = s1;
-    const uintptr_t* u2 = s2;
-    const uintptr_t* end = u1 + (n / sizeof(uintptr_t));
-    while (u1 < end) {
-      if (*u1 != *u2)
-        break;
-      u1++;
-      u2++;
-    }
-    n -= (const void*)u1 - s1;
-    s1 = u1;
-    s2 = u2;
-  }
-
-  while (n--) {
-    unsigned char c1 = *(const unsigned char*)s1++;
-    unsigned char c2 = *(const unsigned char*)s2++;
-    if (c1 != c2)
-      return c1 - c2;
-  }
-
-  return 0;
-}
-
-char* strcpy(char* dest, const char* src)
-{
-  char* d = dest;
-  while ((*d++ = *src++))
-    ;
-  return dest;
-}
-
-long atol(const char* str)
-{
-  long res = 0;
-  int sign = 0;
-
-  while (*str == ' ')
-    str++;
-
-  if (*str == '-' || *str == '+') {
-    sign = *str == '-';
-    str++;
-  }
-
-  while (*str) {
-    res *= 10;
-    res += *str++ - '0';
-  }
-
-  return sign ? -res : res;
-}

Tests/isa/Baremetal-C-programs/vm.c

@@ -1,300 +0,0 @@
-// See LICENSE for license details.
-
-#include <stdint.h>
-#include <string.h>
-#include <stdio.h>
-
-#include "riscv_test.h"
-
-#define SYS_write 64
-
-# define SATP_MODE_CHOICE SATP_MODE_SV39
-
-void trap_entry();
-void pop_tf(trapframe_t*);
-
-extern volatile uint64_t tohost;
-extern volatile uint64_t fromhost;
-
-static void do_tohost(uint64_t tohost_value)
-{
-  while (tohost)
-    fromhost = 0;
-  tohost = tohost_value;
-}
-
-#define pa2kva(pa) ((void*)(pa) - DRAM_BASE - MEGAPAGE_SIZE)
-#define uva2kva(pa) ((void*)(pa) - MEGAPAGE_SIZE)
-
-#define flush_page(addr) asm volatile ("sfence.vma %0" : : "r" (addr) : "memory")
-
-static uint64_t lfsr63(uint64_t x)
-{
-  uint64_t bit = (x ^ (x >> 1)) & 1;
-  return (x >> 1) | (bit << 62);
-}
-
-static void cputchar(int x)
-{
-#if __riscv_xlen == 32
-  // HTIF devices are not supported on RV32, so proxy a write system call
-  volatile uint64_t syscall_struct[8];
-  volatile int buff = x;
-  syscall_struct[0] = SYS_write;
-  syscall_struct[1] = 1;
-  syscall_struct[2] = (uintptr_t)&buff;
-  syscall_struct[3] = 1;
-  do_tohost((uintptr_t)&syscall_struct);
-  // Wait for response as struct has to be read by HTIF
-  while(!fromhost);
-#else
-  do_tohost(0x0101000000000000 | (unsigned char)x);
-#endif
-}
-
-static void cputstring(const char* s)
-{
-  while (*s)
-    cputchar(*s++);
-}
-
-static void terminate(int code)
-{
-  do_tohost(code);
-  while (1);
-}
-
-void wtf()
-{
-  terminate(841);
-}
-
-#define stringify1(x) #x
-#define stringify(x) stringify1(x)
-#define assert(x) do { \
-  if (x) break; \
-  cputstring("Assertion failed: " stringify(x) "\n"); \
-  terminate(3); \
-} while(0)
-
-#define l1pt pt[0]
-#define user_l2pt pt[1]
-# define NPT 4
-# define kernel_l2pt pt[2]
-# define user_llpt pt[3]
-pte_t pt[NPT][PTES_PER_PT] __attribute__((aligned(PGSIZE)));
-
-typedef struct { pte_t addr; void* next; } freelist_t;
-
-freelist_t user_mapping[MAX_TEST_PAGES];
-freelist_t freelist_nodes[MAX_TEST_PAGES];
-freelist_t *freelist_head, *freelist_tail;
-
-void printhex(uint64_t x)
-{
-  char str[17];
-  for (int i = 0; i < 16; i++)
-  {
-    str[15-i] = (x & 0xF) + ((x & 0xF) < 10 ? '0' : 'a'-10);
-    x >>= 4;
-  }
-  str[16] = 0;
-
-  cputstring(str);
-}
-
-static void evict(unsigned long addr)
-{
-  assert(addr >= PGSIZE && addr < MAX_TEST_PAGES * PGSIZE);
-  addr = addr/PGSIZE*PGSIZE;
-
-  freelist_t* node = &user_mapping[addr/PGSIZE];
-  if (node->addr)
-  {
-    // check accessed and dirty bits
-    assert(user_llpt[addr/PGSIZE] & PTE_A);
-    uintptr_t sstatus = set_csr(sstatus, SSTATUS_SUM);
-    if (memcmp((void*)addr, uva2kva(addr), PGSIZE)) {
-      assert(user_llpt[addr/PGSIZE] & PTE_D);
-      memcpy(uva2kva(addr), (void*)addr, PGSIZE);
-    }
-    write_csr(sstatus, sstatus);
-
-    user_mapping[addr/PGSIZE].addr = 0;
-
-    if (freelist_tail == 0)
-      freelist_head = freelist_tail = node;
-    else
-    {
-      freelist_tail->next = node;
-      freelist_tail = node;
-    }
-  }
-}
-
-extern int pf_filter(uintptr_t addr, uintptr_t *pte, int *copy);
-extern int trap_filter(trapframe_t *tf);
-
-void handle_fault(uintptr_t addr, uintptr_t cause)
-{
-  uintptr_t filter_encodings = 0;
-  int copy_page = 1;
-
-  assert(addr >= PGSIZE && addr < MAX_TEST_PAGES * PGSIZE);
-  addr = addr/PGSIZE*PGSIZE;
-
-  if (user_llpt[addr/PGSIZE]) {
-    if (!(user_llpt[addr/PGSIZE] & PTE_A)) {
-      user_llpt[addr/PGSIZE] |= PTE_A;
-    } else {
-      assert(!(user_llpt[addr/PGSIZE] & PTE_D) && cause == CAUSE_STORE_PAGE_FAULT);
-      user_llpt[addr/PGSIZE] |= PTE_D;
-    }
-    flush_page(addr);
-    return;
-  }
-
-  freelist_t* node = freelist_head;
-  assert(node);
-  freelist_head = node->next;
-  if (freelist_head == freelist_tail)
-    freelist_tail = 0;
-
-  uintptr_t new_pte = (node->addr >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V | PTE_U | PTE_R | PTE_W | PTE_X;
-
-  if (pf_filter(addr, &filter_encodings, &copy_page)) {
-      new_pte = (node->addr >> PGSHIFT << PTE_PPN_SHIFT) | filter_encodings;
-  }
-
-  user_llpt[addr/PGSIZE] = new_pte | PTE_A | PTE_D;
-  flush_page(addr);
-
-  assert(user_mapping[addr/PGSIZE].addr == 0);
-  user_mapping[addr/PGSIZE] = *node;
-
-  uintptr_t sstatus = set_csr(sstatus, SSTATUS_SUM);
-  memcpy((void*)addr, uva2kva(addr), PGSIZE);
-  write_csr(sstatus, sstatus);
-
-  user_llpt[addr/PGSIZE] = new_pte;
-  flush_page(addr);
-
-  asm volatile ("fence.i");
-}
-
-void handle_trap(trapframe_t* tf)
-{
-  if (trap_filter(tf)) {
-    pop_tf(tf);
-  }
-
-  if (tf->cause == CAUSE_USER_ECALL)
-  {
-    int n = tf->gpr[10];
-
-    for (long i = 1; i < MAX_TEST_PAGES; i++)
-      evict(i*PGSIZE);
-
-    terminate(n);
-  }
-  else if (tf->cause == CAUSE_ILLEGAL_INSTRUCTION)
-  {
-    assert(tf->epc % 4 == 0);
-
-    int* fssr;
-    asm ("jal %0, 1f; fssr x0; 1:" : "=r"(fssr));
-
-    if (*(int*)tf->epc == *fssr)
-      terminate(1); // FP test on non-FP hardware.  "succeed."
-    else
-      assert(!"illegal instruction");
-    tf->epc += 4;
-  }
-  else if (tf->cause == CAUSE_FETCH_PAGE_FAULT || tf->cause == CAUSE_LOAD_PAGE_FAULT || tf->cause == CAUSE_STORE_PAGE_FAULT)
-    handle_fault(tf->badvaddr, tf->cause);
-  else
-    assert(!"unexpected exception");
-
-  pop_tf(tf);
-}
-
-static void coherence_torture()
-{
-  // cause coherence misses without affecting program semantics
-  uint64_t random = ENTROPY;
-  while (1) {
-    uintptr_t paddr = DRAM_BASE + ((random % (2 * (MAX_TEST_PAGES + 1) * PGSIZE)) & -4);
-#ifdef __riscv_atomic
-    if (random & 1) // perform a no-op write
-      asm volatile ("amoadd.w zero, zero, (%0)" :: "r"(paddr));
-    else // perform a read
-#endif
-      asm volatile ("lw zero, (%0)" :: "r"(paddr));
-    random = lfsr63(random);
-  }
-}
-
-void vm_boot(uintptr_t test_addr)
-{
-  uint64_t random = ENTROPY;
-  if (read_csr(mhartid) > 0)
-    coherence_torture();
-
-  _Static_assert(SIZEOF_TRAPFRAME_T == sizeof(trapframe_t), "???");
-
-#if (MAX_TEST_PAGES > PTES_PER_PT) || (DRAM_BASE % MEGAPAGE_SIZE) != 0
-# error
-#endif
-  // map user to lowermost megapage
-  l1pt[0] = ((pte_t)user_l2pt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V;
-  // map kernel to uppermost megapage
-  l1pt[PTES_PER_PT-1] = ((pte_t)kernel_l2pt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V;
-  kernel_l2pt[PTES_PER_PT-1] = (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_R | PTE_W | PTE_X | PTE_A | PTE_D;
-  user_l2pt[0] = ((pte_t)user_llpt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V;
-  uintptr_t vm_choice = SATP_MODE_CHOICE;
-  uintptr_t satp_value = ((uintptr_t)l1pt >> PGSHIFT)
-                        | (vm_choice * (SATP_MODE & ~(SATP_MODE<<1)));
-  write_csr(satp, satp_value);
-  if (read_csr(satp) != satp_value)
-    assert(!"unsupported satp mode");
-  flush_page(DRAM_BASE);
-
-  // Set up PMPs if present, ignoring illegal instruction trap if not.
-  uintptr_t pmpc = PMP_NAPOT | PMP_R | PMP_W | PMP_X;
-  uintptr_t pmpa = ((uintptr_t)1 << (__riscv_xlen == 32 ? 31 : 53)) - 1;
-  asm volatile ("la t0, 1f\n\t"
-                "csrrw t0, mtvec, t0\n\t"
-                "csrw pmpaddr0, %1\n\t"
-                "csrw pmpcfg0, %0\n\t"
-                ".align 2\n\t"
-                "1: csrw mtvec, t0"
-                : : "r" (pmpc), "r" (pmpa) : "t0");
-
-  // set up supervisor trap handling
-  write_csr(stvec, pa2kva(trap_entry));
-  write_csr(sscratch, pa2kva(read_csr(mscratch)));
-  write_csr(medeleg,
-    (1 << CAUSE_USER_ECALL) |
-    (1 << CAUSE_FETCH_PAGE_FAULT) |
-    (1 << CAUSE_LOAD_PAGE_FAULT) |
-    (1 << CAUSE_STORE_PAGE_FAULT));
-  // FPU on; accelerator on; vector unit on
-  write_csr(mstatus, MSTATUS_FS | MSTATUS_XS | MSTATUS_VS);
-  write_csr(mie, 0);
-
-  random = 1 + (random % MAX_TEST_PAGES);
-  freelist_head = pa2kva((void*)&freelist_nodes[0]);
-  freelist_tail = pa2kva(&freelist_nodes[MAX_TEST_PAGES-1]);
-  for (long i = 0; i < MAX_TEST_PAGES; i++)
-  {
-    freelist_nodes[i].addr = DRAM_BASE + (MAX_TEST_PAGES + random)*PGSIZE;
-    freelist_nodes[i].next = pa2kva(&freelist_nodes[i+1]);
-    random = LFSR_NEXT(random);
-  }
-  freelist_nodes[MAX_TEST_PAGES-1].next = 0;
-
-  trapframe_t tf;
-  memset(&tf, 0, sizeof(tf));
-  tf.epc = test_addr - DRAM_BASE;
-  pop_tf(&tf);
-}

Tests/isa/Cheri.S

@@ -1,37 +0,0 @@
-    .section .bss
-    .align 6              # 64-byte alignment helps bounds encoding
-buffer:
-    .space 64
-
-    .section .text
-    .globl _start
-_start:
-
-    # ------------------------------------------------------------
-    # 1. Create capability to buffer using DDC (c0)
-    # ------------------------------------------------------------
-    la        t0, buffer
-    cincoffset c1, c0, t0     # c1 -> buffer capability
-
-    # ------------------------------------------------------------
-    # 2. Set bounds to first 16 bytes
-    # ------------------------------------------------------------
-    li        t1, 16
-    csetbounds c2, c1, t1     # c2 = bounded capability
-
-    # ------------------------------------------------------------
-    # 3. Store value 0x42 into buffer[0] using capability
-    # ------------------------------------------------------------
-    li        t2, 0x42
-    csb       t2, 0(c2)       # capability store byte
-
-    # ------------------------------------------------------------
-    # 4. Load the value back from buffer[0]
-    # ------------------------------------------------------------
-    clbu      t3, 0(c2)       # t3 should now contain 0x42
-
-    # ------------------------------------------------------------
-    # 5. Infinite loop (bare-metal halt)
-    # ------------------------------------------------------------
-1:
-    j 1b

Tests/isa/CheriPage.S

@@ -1,129 +0,0 @@
-.option norvc
-.option norelax
-
-# ==================================================
-# Text section
-# ==================================================
-.section .text
-.globl _start
-_start:
-
-vm_boot:
-    # Only hart 0 runs
-    csrr    a0, mhartid
-    bnez    a0, hang
-
-    # --------------------------------------------------
-    # root_pt[0] -> l1_pt
-    # --------------------------------------------------
-    cllc    c0, l1_pt
-    li      t2, 4096
-    csetbounds c0, c0, t2
-
-    cgetaddr t0, c0
-    srli    t0, t0, 12
-    slli    t0, t0, 10
-    ori     t0, t0, 0x1      # V bit
-
-    cllc    c1, root_pt
-    li      t2, 4096
-    csetbounds c1, c1, t2
-    sd      t0, 0(c1)
-
-    # --------------------------------------------------
-    # l1_pt[0] -> l0_pt
-    # --------------------------------------------------
-    cllc    c0, l0_pt
-    li      t2, 4096
-    csetbounds c0, c0, t2
-
-    cgetaddr t0, c0
-    srli    t0, t0, 12
-    slli    t0, t0, 10
-    ori     t0, t0, 0x1      # V bit
-
-    cllc    c1, l1_pt
-    li      t2, 4096
-    csetbounds c1, c1, t2
-    sd      t0, 0(c1)
-
-    # --------------------------------------------------
-    # l0_pt[0] -> leaf (RWX)
-    # --------------------------------------------------
-    li      t0, (1<<0)|(1<<1)|(1<<2)|(1<<3)|(1<<6)  # V R W X A
-
-    cllc    c1, l0_pt
-    li      t2, 4096
-    csetbounds c1, c1, t2
-    sd      t0, 0(c1)
-
-    # --------------------------------------------------
-    # Enable Sv39 paging
-    # --------------------------------------------------
-    cllc    c0, root_pt
-    li      t2, 4096
-    csetbounds c0, c0, t2
-
-    cgetaddr t0, c0
-    srli    t0, t0, 12
-    li      t1, (8 << 60)      # MODE = Sv39
-    or      t0, t0, t1
-    csrw    satp, t0
-    sfence.vma zero, zero
-
-    # --------------------------------------------------
-    # Safe data access
-    # --------------------------------------------------
-    cllc    c2, test_buf
-    li      t2, 16
-    csetbounds c2, c2, t2
-
-    li      t3, 0x1122334455667788
-    sd      t3, 0(c2)
-    ld      t4, 0(c2)
-    bne     t3, t4, hang
-
-    # --------------------------------------------------
-    # Signal success
-    # --------------------------------------------------
-    cllc    c0, tohost
-    li      t2, 8
-    csetbounds c0, c0, t2
-    li      t1, 1
-    sd      t1, 0(c0)
-
-hang:
-    wfi
-    j hang
-
-# ==================================================
-# Data section (aligned, contiguous, no .org)
-# ==================================================
-.section .data
-.align 12
-.globl root_pt
-root_pt:
-    .zero 4096      # Root page table
-
-.align 12
-.globl l1_pt
-l1_pt:
-    .zero 4096      # Level 1 page table
-
-.align 12
-.globl l0_pt
-l0_pt:
-    .zero 4096      # Level 0 page table
-
-.align 3
-.globl test_buf
-test_buf:
-    .zero 16        # Test buffer
-
-.globl tohost
-tohost:
-    .dword 0
-
-.globl fromhost
-fromhost:
-    .dword 0

Tests/isa/MemoryAllocator.S

@@ -1,177 +0,0 @@
-.option norvc
-.option norelax
-
-# ==================================================
-# Constants
-# ==================================================
-.equ PTE_V, 0x001
-.equ PTE_R, 0x002
-.equ PTE_W, 0x004
-.equ PTE_X, 0x008
-.equ PTE_A, 0x040
-.equ PTE_D, 0x080
-
-.equ SATP_MODE_SV39, (8 << 60)
-
-# ==================================================
-# Text
-# ==================================================
-.section .text
-.globl _start
-
-_start:
-    # only hart 0
-    csrr a0, mhartid
-    bnez a0, hang
-
-    # install trap vector (required)
-    la   t0, trap_vector
-    csrw stvec, t0
-
-    # --------------------------------------------------
-    # Build page tables (Sv39 identity map 1 GiB)
-    # --------------------------------------------------
-
-    # root_pt[0] -> l1_pt
-    la   t0, l1_pt
-    srli t0, t0, 12
-    slli t0, t0, 10
-    ori  t0, t0, PTE_V
-    la   t1, root_pt
-    sd   t0, 0(t1)
-
-    # l1_pt[0] -> l0_pt
-    la   t0, l0_pt
-    srli t0, t0, 12
-    slli t0, t0, 10
-    ori  t0, t0, PTE_V
-    la   t1, l1_pt
-    sd   t0, 0(t1)
-
-    # l0_pt[0] = 1GiB RWX identity leaf
-    li   t0, (PTE_V|PTE_R|PTE_W|PTE_X|PTE_A|PTE_D)
-    la   t1, l0_pt
-    sd   t0, 0(t1)
-
-    # --------------------------------------------------
-    # Enable Sv39
-    # --------------------------------------------------
-    la   t0, root_pt
-    srli t0, t0, 12
-    li   t1, SATP_MODE_SV39
-    or   t0, t0, t1
-    csrw satp, t0
-    # sfence.vma zero, zero
-
-    # --------------------------------------------------
-    # Init allocator
-    # --------------------------------------------------
-    la   t0, heap_base
-    la   t1, heap_ptr
-    sd   t0, 0(t1)
-
-    la   t0, free_list
-    sd   zero, 0(t0)
-
-    # --------------------------------------------------
-    # Allocate → free → reuse test
-    # --------------------------------------------------
-    li   a0, 16
-    call alloc
-    mv   s1, a0
-
-    li   t0, 0x1122334455667788
-    sd   t0, 0(s1)
-
-    mv   a0, s1
-    call free
-
-    li   a0, 16
-    call alloc
-    mv   s2, a0
-
-    ld   t1, 0(s2)
-    li   t0, 0x1122334455667788
-    bne  t1, t0, hang
-
-    # success
-    la   t0, tohost
-    li   t1, 1
-    sd   t1, 0(t0)
-
-hang:
-    wfi
-    j hang
-
-# ==================================================
-# Minimal trap handler (required)
-# ==================================================
-.align 2
-trap_vector:
-    csrr t0, scause
-    j hang
-
-# ==================================================
-# alloc(size)
-# ==================================================
-.globl alloc
-alloc:
-    la   t0, free_list
-    ld   t1, 0(t0)
-    beqz t1, alloc_bump
-
-    ld   t2, 0(t1)
-    sd   t2, 0(t0)
-    addi a0, t1, 8
-    ret
-
-alloc_bump:
-    la   t0, heap_ptr
-    ld   t1, 0(t0)
-    addi t2, a0, 8
-    add  t3, t1, t2
-    la   t4, heap_end
-    bgtu t3, t4, hang
-    sd   t3, 0(t0)
-    addi a0, t1, 8
-    ret
-
-# ==================================================
-# free(ptr)
-# ==================================================
-.globl free
-free:
-    addi t0, a0, -8
-    la   t1, free_list
-    ld   t2, 0(t1)
-    sd   t2, 0(t0)
-    sd   t0, 0(t1)
-    ret
-
-# ==================================================
-# Data (NO .bss)
-# ==================================================
-.section .data
-.align 3
-
-.globl tohost
-.globl fromhost
-tohost:   .dword 0
-fromhost: .dword 0
-
-.globl heap_ptr
-.globl free_list
-heap_ptr:  .dword 0
-free_list: .dword 0
-
-.align 12
-heap_base:
-    .zero 4096
-heap_end:
-
-.align 12
-root_pt: .zero 4096
-.align 12
-l1_pt:   .zero 4096
-.align 12
-l0_pt:   .zero 4096

Tests/isa/PageCompileSteps.txt

@@ -1,4 +1,3 @@
- scp Tests/isa/MemoryAllocator.S home:/home/akilan/Documents/cheri/riscv/riscv/bin
 ./riscv64-unknown-elf-gcc -nostdlib -nostartfiles   -Wl,-Ttext=0x80000000   Page.S   -o Page.o
 ./riscv64-unknown-elf-objcopy --remove-section .bss Page.o Page
 # Copy file

Tests/isa/PageRead.S

@@ -1,230 +0,0 @@
-.option norvc
-.option norelax
-
-# ==================================================
-# Text section
-# ==================================================
-.section .text
-.globl _start
-.globl vm_boot
-
-_start:
-vm_boot:
-    # --------------------------------------------------
-    # Only hart 0 runs
-    # --------------------------------------------------
-    csrr    a0, mhartid
-    bnez    a0, hang
-
-    # --------------------------------------------------
-    # Build page tables
-    # --------------------------------------------------
-
-#
-# Page table setup (Sv39) — binary + hex example
-#
-# Purpose:
-#   Build a VALID page table entry (PTE) in the root page table
-#   that points to the next-level page table (l1_pt).
-#
-# Assume:
-#   l1_pt physical address =
-#     binary: 00000000 10000000 01000000 00110000 00000000
-#     hex:    0x0000000080403000
-#     (page aligned, lower 12 bits = 0)
-#
-# Step-by-step instruction meaning:
-#
-#   la   t0, l1_pt
-#        Load physical address of l1_pt.
-#
-#        t0 =
-#          binary: 00000000 10000000 01000000 00110000 00000000
-#          hex:    0x0000000080403000
-#
-#   srli t0, t0, 12
-#        Drop 12-bit page offset → extract Physical Page Number (PPN).
-#
-#        t0 (PPN) =
-#          binary: 00000000 00000000 10000000 01000000 0011
-#          hex:    0x0000000000080403
-#
-#   slli t0, t0, 10
-#        Shift PPN into PTE bit positions [63:10].
-#        Bits [9:0] are flags.
-#
-#        t0 =
-#          binary: 00000000 00000000 10000000 01000000 0011 0000000000
-#          hex:    0x0000000020100C00
-#
-#   ori  t0, t0, 1
-#        Set bit 0 (V = Valid).
-#
-#        t0 (final PTE) =
-#          binary: 00000000 00000000 10000000 01000000 0011 0000000001
-#          hex:    0x0000000020100C01
-#
-# Memory effect:
-#
-#   root_pt[0] =
-#     bit index:
-#       63                              10 9        0
-#     +----------------------------------+----------+
-#     |   PPN = 0x0000000000080403       | V = 1    |
-#     +----------------------------------+----------+
-#
-#     binary: 00000000 00000000 10000000 01000000 0011 0000000001
-#     hex:    0x0000000020100C01
-#
-# Result:
-#   Root page table entry 0 is VALID and points to l1_pt.
-#   The MMU uses this entry to continue the Sv39 page-table walk.
-#
-
-
-    # root_pt[0] -> l1_pt
-    la      t0, l1_pt
-    srli    t0, t0, 12          # PPN
-    slli    t0, t0, 10          # PTE format
-    ori     t0, t0, 0x1         # V
-    la      t1, root_pt
-    sd      t0, 0(t1)
-
-    # l1_pt[0] -> l0_pt
-    la      t0, l0_pt
-    srli    t0, t0, 12  
-    slli    t0, t0, 10
-    ori     t0, t0, 0x1         # V
-    la      t1, l1_pt
-    sd      t0, 0(t1)
-
-    # l0_pt[0] -> identity mapping (RWX)
-    li      t0, (1<<0)|(1<<1)|(1<<2)|(1<<3)|(1<<6)  # V R W X A
-    la      t1, l0_pt
-    sd      t0, 0(t1)
-
-    # --------------------------------------------------
-    # Enable Sv39 paging
-    # --------------------------------------------------
-
-# Enable virtual memory (Sv39) — SATP setup diagram (binary)
-#
-# Assume:
-#   root_pt physical address =
-#     00000000 10000000 01000000 00010000 00000000
-#     (4 KB aligned, lower 12 bits = 0)
-#
-# Instruction flow:
-#
-#   la   t0, root_pt
-#        t0 =
-#        00000000 10000000 01000000 00010000 00000000
-#
-#   srli t0, t0, 12            ; extract PPN
-#        t0 (PPN) =
-#        00000000 00000000 10000000 01000000 0001
-#
-#   li   t1, (8 << 60)         ; MODE = Sv39
-#        t1 =
-#        1000 0000000000000000000000000000000000000000000000000000
-#        ^^^^
-#        MODE[63:60] = 1000 (Sv39)
-#
-#   or   t0, t0, t1
-#        satp value =
-#        1000 0000000000000000000000000000000010000000010000000001
-#        |<-- MODE -->|<----------- ASID ---------->|<---- PPN ---->|
-#
-#   csrw satp, t0
-#        satp register loaded:
-#
-#        63   60 59                              44 43             0
-#        +------+----------------------------------+----------------+
-#        |1000  |0000000000000000                  |0000000010000000010000000001|
-#        +------+----------------------------------+----------------+
-#         MODE=Sv39        ASID=0                     root_pt PPN
-#
-#   sfence.vma zero, zero
-#        Flush all TLB entries so new page tables are used
-#
-# Meaning:
-#   - Virtual memory enabled in Sv39 mode
-#   - Root page table base = root_pt
-#   - ASID = 0
-#   - MMU now performs 3-level page table walks
-#
-
-    la      t0, root_pt
-    srli    t0, t0, 12
-    li      t1, (8 << 60)       # MODE=Sv39
-    or      t0, t0, t1
-    csrw    satp, t0
-    sfence.vma zero, zero
-
-    # --------------------------------------------------
-    # Write data to memory (safe area)
-    # --------------------------------------------------
-    la      t2, test_buf
-    li      t3, 0x1122334455667788
-    sd      t3, 0(t2)
-
-    # --------------------------------------------------
-    # Read data back
-    # --------------------------------------------------
-    ld      t4, 0(t2)
-
-    # Optional check (simple)
-    bne     t3, t4, hang
-
-    # --------------------------------------------------
-    # Signal success
-    # --------------------------------------------------
-    la      t0, tohost
-    li      t1, 1
-    sd      t1, 0(t0)
-
-hang:
-    wfi
-    j hang
-
-# ==================================================
-# Required test symbol
-# ==================================================
-.globl exit
-exit:
-    j exit
-
-# ==================================================
-# Data section
-# ==================================================
-.section .data
-.align 3
-
-.globl tohost
-.globl fromhost
-tohost:
-    .dword 0
-fromhost:
-    .dword 0
-
-# --------------------------------------------------
-# Test buffer (safe data memory)
-# --------------------------------------------------
-.align 3
-test_buf:
-    .zero 16
-
-# --------------------------------------------------
-# Page tables (must be 4 KiB each)
-# --------------------------------------------------
-.align 12
-root_pt:
-    .zero 4096
-
-.align 12
-l1_pt:
-    .zero 4096
-
-.align 12
-l0_pt:
-    .zero 4096

Tests/isa/PageTableTest.S

@@ -12,7 +12,7 @@ _start:
 vm_boot:
     # Only hart 0
     csrr    a0, mhartid
-    bnez    a0, hang.   
+    bnez    a0, hang
 
     # --------------------------------------------------
     # Build page table entries

builds/RV64ACDFIMSUxCHERI_Toooba_RVFI_DII_bluesim/test.txt

@@ -0,0 +1,43 @@
+make -C  ../../Tests/elf_to_hex
+make[1]: Entering directory '/Users/akilan/Documents/Cheri/Test/Reverse/Test/Toooba/Tests/elf_to_hex'
+make[1]: 'elf_to_hex' is up to date.
+make[1]: Leaving directory '/Users/akilan/Documents/Cheri/Test/Reverse/Test/Toooba/Tests/elf_to_hex'
+../../Tests/elf_to_hex/elf_to_hex  ../../Tests/isa/rv64ui-p-add  Mem.hex
+c_mem_load_elf: ../../Tests/isa/rv64ui-p-add is a 64-bit ELF file
+Section .text.init      : addr         80000000 to addr         80000644; size 0x     644 (= 1604) bytes
+Section .tohost         : addr         80001000 to addr         80001048; size 0x      48 (= 72) bytes
+Section .riscv.attributes: Ignored
+Section .symtab         : Searching for addresses of '_start', 'exit' and 'tohost' symbols
+Writing symbols to:    symbol_table.txt
+    No 'exit' label found
+Section .strtab         : Ignored
+Section .shstrtab       : Ignored
+Min addr:                    80000000 (hex)
+Max addr:                    80001047 (hex)
+Writing mem hex to file 'Mem.hex'
+Subtracting 0x80000000 base from addresses
+./exe_HW_sim  +v1  +tohost
+================================================================
+Bluespec RISC-V standalone system simulation v1.2
+Copyright (c) 2017-2018 Bluespec, Inc. All Rights Reserved.
+================================================================
+2: top.dut_soc_top.rl_reset_start_initial ...
+---- allocated socket for RVFI_DII
+---- RVFI_DII_PORT environment variable not defined, using default port 5001 instead
+---- RVFI_DII socket listening on port 5001
+req addr: 'h0000000000000000, zeroed_0_start: 'h0000000000000000-'h0000000000040000, zeroed_1_start: 'h0000000001f80000-'h0000000001fffff8
+req addr: 'h0000000000000000, zeroed_0_start: 'h0000000000000000-'h0000000000040000, zeroed_1_start: 'h0000000001f80000-'h0000000001fffff8
+74: Mem_Controller.set_addr_map: addr_base 0x80000000 addr_lim 0xc0000000
+  SoC address map:
+  Boot ROM:        0x1000 .. 0x2000
+  Mem0 Controller: 0x80000000 .. 0xc0000000
+  UART0:           0xc0000000 .. 0xc0000080
+74: top.dut_soc_top.rl_reset_complete_initial
+INFO: watch_tohost 1, tohost_addr = 0x80001000, fromhost_addr = 0x0
+75: top.dut_soc_top.method start (tohost 80001000, fromhost 0)
+101: top.dut_soc_top.rl_step_0, n = 0, do_release
+101: top.dut_soc_top do_release(restartRunning: True, to_host_addr: 0)
+101: top.dut_soc_top.proc.method start: startpc 80000000, tohostAddr 0, fromhostAddr 0
+102: top.dut_soc_top.rl_ctrl_req
+102: top.dut_soc_top.proc.method start: startpc 80000000, tohostAddr 80001000, fromhostAddr 0
+102: top.dut_soc_top do_release(restartRunning: True, to_host_addr: 80001000)

builds/RV64ACDFIMSUxCHERI_Toooba_RVFI_DII_verilator/Mem.hex

@@ -0,0 +1,134 @@
+@0000000    // raw_mem addr;  byte addr: 00000000
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000000;  byte addr 00000000
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000001;  byte addr 00000020
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000002;  byte addr 00000040
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000003;  byte addr 00000060
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000004;  byte addr 00000080
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000005;  byte addr 000000a0
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000006;  byte addr 000000c0
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000007;  byte addr 000000e0
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000008;  byte addr 00000100
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000009;  byte addr 00000120
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 0000000a;  byte addr 00000140
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 0000000b;  byte addr 00000160
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 0000000c;  byte addr 00000180
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 0000000d;  byte addr 000001a0
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 0000000e;  byte addr 000001c0
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 0000000f;  byte addr 000001e0
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000010;  byte addr 00000200
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000011;  byte addr 00000220
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000012;  byte addr 00000240
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000013;  byte addr 00000260
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000014;  byte addr 00000280
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000015;  byte addr 000002a0
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000016;  byte addr 000002c0
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000017;  byte addr 000002e0
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000018;  byte addr 00000300
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000019;  byte addr 00000320
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 0000001a;  byte addr 00000340
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 0000001b;  byte addr 00000360
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 0000001c;  byte addr 00000380
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 0000001d;  byte addr 000003a0
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 0000001e;  byte addr 000003c0
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 0000001f;  byte addr 000003e0
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000020;  byte addr 00000400
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000021;  byte addr 00000420
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000022;  byte addr 00000440
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000023;  byte addr 00000460
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000024;  byte addr 00000480
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000025;  byte addr 000004a0
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000026;  byte addr 000004c0
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000027;  byte addr 000004e0
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000028;  byte addr 00000500
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000029;  byte addr 00000520
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 0000002a;  byte addr 00000540
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 0000002b;  byte addr 00000560
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 0000002c;  byte addr 00000580
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 0000002d;  byte addr 000005a0
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 0000002e;  byte addr 000005c0
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 0000002f;  byte addr 000005e0
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000030;  byte addr 00000600
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000031;  byte addr 00000620
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000032;  byte addr 00000640
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000033;  byte addr 00000660
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000034;  byte addr 00000680
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000035;  byte addr 000006a0
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000036;  byte addr 000006c0
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000037;  byte addr 000006e0
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000038;  byte addr 00000700
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000039;  byte addr 00000720
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 0000003a;  byte addr 00000740
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 0000003b;  byte addr 00000760
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 0000003c;  byte addr 00000780
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 0000003d;  byte addr 000007a0
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 0000003e;  byte addr 000007c0
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 0000003f;  byte addr 000007e0
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000040;  byte addr 00000800
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000041;  byte addr 00000820
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000042;  byte addr 00000840
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000043;  byte addr 00000860
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000044;  byte addr 00000880
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000045;  byte addr 000008a0
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000046;  byte addr 000008c0
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000047;  byte addr 000008e0
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000048;  byte addr 00000900
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000049;  byte addr 00000920
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 0000004a;  byte addr 00000940
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 0000004b;  byte addr 00000960
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 0000004c;  byte addr 00000980
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 0000004d;  byte addr 000009a0
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 0000004e;  byte addr 000009c0
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 0000004f;  byte addr 000009e0
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000050;  byte addr 00000a00
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000051;  byte addr 00000a20
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000052;  byte addr 00000a40
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000053;  byte addr 00000a60
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000054;  byte addr 00000a80
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000055;  byte addr 00000aa0
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000056;  byte addr 00000ac0
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000057;  byte addr 00000ae0
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000058;  byte addr 00000b00
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000059;  byte addr 00000b20
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 0000005a;  byte addr 00000b40
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 0000005b;  byte addr 00000b60
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 0000005c;  byte addr 00000b80
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 0000005d;  byte addr 00000ba0
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 0000005e;  byte addr 00000bc0
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 0000005f;  byte addr 00000be0
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000060;  byte addr 00000c00
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000061;  byte addr 00000c20
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000062;  byte addr 00000c40
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000063;  byte addr 00000c60
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000064;  byte addr 00000c80
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000065;  byte addr 00000ca0
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000066;  byte addr 00000cc0
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000067;  byte addr 00000ce0
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000068;  byte addr 00000d00
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000069;  byte addr 00000d20
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 0000006a;  byte addr 00000d40
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 0000006b;  byte addr 00000d60
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 0000006c;  byte addr 00000d80
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 0000006d;  byte addr 00000da0
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 0000006e;  byte addr 00000dc0
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 0000006f;  byte addr 00000de0
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000070;  byte addr 00000e00
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000071;  byte addr 00000e20
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000072;  byte addr 00000e40
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000073;  byte addr 00000e60
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000074;  byte addr 00000e80
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000075;  byte addr 00000ea0
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000076;  byte addr 00000ec0
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000077;  byte addr 00000ee0
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000078;  byte addr 00000f00
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000079;  byte addr 00000f20
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 0000007a;  byte addr 00000f40
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 0000007b;  byte addr 00000f60
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 0000007c;  byte addr 00000f80
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 0000007d;  byte addr 00000fa0
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 0000007e;  byte addr 00000fc0
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 0000007f;  byte addr 00000fe0
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000080;  byte addr 00001000
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000081;  byte addr 00001020
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 00000082;  byte addr 00001040
+@07fffff    // last raw_mem addr;  byte addr: 0fffffe0
+0000000000000000000000000000000000000000000000000000000000000000    // raw_mem addr 007fffff;  byte addr 0fffffe0

builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/Makefile

@@ -9,13 +9,9 @@ BSC_COMPILATION_FLAGS += -verbose
 # Default ISA test
 
 # TEST ?= rv64ui-p-add
-TEST ?= rv64um-v-mulw
+# TEST ?= rv64um-v-mulw
 # TEST ?= Page
-# TEST ?= PageReadWrite
-# TEST ?= CheriPage
-# TEST ?= MemoryAllocator
-# TEST = rv64ui-v-blt
-# TEST = string
+TEST ?= PageReadWrite
 
 #================================================================
 # Parameter settings for MIT RISCY, setup paths etc. for Include_Common

builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/exe_HW_sim

@@ -1,12 +0,0 @@
-#!/bin/sh
-
-BLUESPECDIR=`echo 'puts $env(BLUESPECDIR)' | bluetcl`
-
-for arg in $@
-do
-  if (test "$arg" = "-h")
-  then
-    exec $BLUESPECDIR/tcllib/bluespec/bluesim.tcl $0.so mkTop_HW_Side --script_name `basename $0` -h
-  fi
-done
-exec $BLUESPECDIR/tcllib/bluespec/bluesim.tcl $0.so mkTop_HW_Side --script_name `basename $0` --creation_time 1770243680 "$@"

builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/test.txt

@@ -0,0 +1,345 @@
+make -C  ../../Tests/elf_to_hex
+make[1]: Entering directory '/Users/akilan/Documents/Cheri/Test/Reverse/Test/Toooba/Tests/elf_to_hex'
+make[1]: 'elf_to_hex' is up to date.
+make[1]: Leaving directory '/Users/akilan/Documents/Cheri/Test/Reverse/Test/Toooba/Tests/elf_to_hex'
+../../Tests/elf_to_hex/elf_to_hex  ../../Tests/isa/PageReadWrite  Mem.hex
+c_mem_load_elf: ../../Tests/isa/PageReadWrite is a 64-bit ELF file
+Section .text           : addr         80000000 to addr         800000c8; size 0x      c8 (= 200) bytes
+Section .data           : addr         80002000 to addr         80006000; size 0x    4000 (= 16384) bytes
+Section .riscv.attributes: Ignored
+Section .symtab         : Searching for addresses of '_start', 'exit' and 'tohost' symbols
+Writing symbols to:    symbol_table.txt
+Section .strtab         : Ignored
+Section .shstrtab       : Ignored
+Min addr:                    80000000 (hex)
+Max addr:                    80005fff (hex)
+Writing mem hex to file 'Mem.hex'
+Subtracting 0x80000000 base from addresses
+./exe_HW_sim  +v1  +tohost
+Warning: file 'Mem.hex' for memory 'rf' has a gap at addresses 768 to 33554430.
+1: top.soc_top.rl_reset_start_initial ...
+11: Mem_Controller.set_addr_map: addr_base 0x80000000 addr_lim 0xc0000000
+  SoC address map:
+  Boot ROM:        0x1000 .. 0x2000
+  Mem0 Controller: 0x80000000 .. 0xc0000000
+  UART0:           0xc0000000 .. 0xc0000080
+11: top.soc_top.rl_reset_complete_initial
+================================================================
+Bluespec RISC-V standalone system simulation v1.2
+Copyright (c) 2017-2019 Bluespec, Inc. All Rights Reserved.
+================================================================
+INFO: watch_tohost 1, tohost_addr = 0x80002000, fromhost_addr = 0x0
+12: top.soc_top.method start (tohost 80002000, fromhost 0)
+100: top.soc_top.rl_step_0, n = 0, do_release
+100: top.soc_top do_release(restartRunning: True, to_host_addr: 0)
+100: top.soc_top.corew_proc.method start: startpc 1000, tohostAddr 0, fromhostAddr 0
+101: top.soc_top.rl_ctrl_req
+101: top.soc_top.corew_proc.method start: startpc 1000, tohostAddr 80002000, fromhostAddr 0
+101: top.soc_top do_release(restartRunning: True, to_host_addr: 80002000)
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000020 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+[RFile] wr_          1: r 40 <= 0000000000000400000000001fffff44000000
+[RFile] wr_          0: r 41 <= 0000000000000408000000001fffff44000000
+instret:0  PC:0x1ffff0000000000000000000000001000  instr:0x00000297   iType:Auipc    [doCommitNormalInst [0]]        167
+instret:1  PC:0x1ffff0000000000000000000000001004  instr:0x02028593   iType:Alu    [doCommitNormalInst [0]]        168
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Csr, execFunc: tagged Alu Csrs, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Valid csrAddrMHARTID, scr: tagged Invalid , imm: tagged Invalid  }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+[RFile] wr_          0: r 42 <= 0000000000000000000000001fffff44000000
+instret:2  PC:0x1ffff0000000000000000000000001008  instr:0xf1402573   iType:Csr    [doCommitSystemInst]        224
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000018, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+                3340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000018, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+                3350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000018, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
+                3360 : [doExeMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000018, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000000001000 o: 'h0000000000001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000000001018 o: 'h0000000000001018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, shiftBEData: <V False False False False False False False False True True True True True True True True  > }, spec_bits: 'h000 }
+                3370 : [doFinishMem] DTlbResp { resp: <'h0000000000001018,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True  >, vaddr: v: True a: 'h0000000000001018 o: 'h0000000000001018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000000001018, check_high: 'h00000000000001020, check_inclusive: True } }, specBits: 'h000 }
+outside TLB
+[doDeqLdQ_MMIO_issue] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000000001018, isMMIO: True, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True  >, fault: tagged Invalid , allowCap: False, killed: tagged Invalid  }; MMIOCRq { addr: 'h0000000000001018, func: tagged Ld , byteEn: <V False False False False False False False False True True True True True True True True  >, data: TaggedData { tag: , data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, loadTags: False }
+[RFile] wr_          3: r 43 <= 0000000020000000000000001fffff44000000
+[doDeqLdQ_MMIO_deq] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000000001018, isMMIO: True, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True  >, fault: tagged Invalid , allowCap: False, killed: tagged Invalid  }; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000080000000  > }; TaggedData { tag: False, data: <V 'h0000000080000000 'h0000000000000000  > }
+instret:3  PC:0x1ffff000000000000000000000000100c  instr:0x0182b283   iType:Ld    [doCommitNormalInst [0]]        403
+[ALU redirect -           1] 'h1ffff0000000000000000000080000000; 'h0; InstTag { way: 'h0, ptr: 'h02, t: 'h04 }
+[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } ; 'h1 ; 'h0 ; <V 'h03 'h02  > ; <V 'h02 'h02  > ; <V <V False False True False False False False False False False False False False False False False False False False False False False False False False False False False False False False False  > <V False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False  >  > ; <V <V False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False  > <V False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False  >  > ; 'h1 ; <V 'h03 'h02  > ; <V 'h00 'h00  >
+instret:4  PC:0x1ffff0000000000000000000000001010  instr:0x00028067   iType:Jr    [doCommitNormalInst [0]]        408
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Csr, execFunc: tagged Alu Csrs, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Valid csrAddrMHARTID, scr: tagged Invalid , imm: tagged Invalid  }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+[RFile] wr_          0: r 45 <= 0000000000000000000000001fffff44000000
+instret:5  PC:0x1ffff0000000000000000000080000000  instr:0xf1402573   iType:Csr    [doCommitSystemInst]       1155
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Neq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h000000b8 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h002 }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Srl, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h48, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffff8 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h48, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Or, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h06, rn2 'h06}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffe4 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00003000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+[RFile] wr_          0: r 47 <= 0000000020001002000000001fffff44000000
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00005000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h06, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
+[RFile] wr_          1: r 48 <= 0000000020001000000000001fffff44000000
+instret:6  PC:0x1ffff0000000000000000000080000004  instr:0x0a051c63   iType:Br    [doCommitNormalInst [0]]       1167
+instret:7  PC:0x1ffff0000000000000000000080000008  instr:0x00004297   iType:Auipc    [doCommitNormalInst [1]]       1167
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Srl, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h18}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffd8 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
+[RFile] wr_          0: r 49 <= 0000000000020001000000001fffff44000000
+instret:8  PC:0x1ffff000000000000000000008000000c  instr:0xff828293   iType:Alu    [doCommitNormalInst [0]]       1168
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Or, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
+[RFile] wr_          1: r 4a <= 0000000008000400000000001fffff44000000
+               11690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h06, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+instret:9  PC:0x1ffff0000000000000000000080000010  instr:0x00c2d293   iType:Alu    [doCommitNormalInst [0]]       1169
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+[RFile] wr_          0: r 4b <= 0000000008000400400000001fffff44000000
+[RFile] wr_          1: r 4c <= 0000000020000c07000000001fffff44000000
+               11700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h06, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
+instret:10  PC:0x1ffff0000000000000000000080000014  instr:0x00a29293   iType:Alu    [doCommitNormalInst [0]]       1170
+[RFile] wr_          0: r 4d <= 0000000020000c00000000001fffff44000000
+[RFile] wr_          1: r 4f <= 000000002000140a000000001fffff44000000
+               11710 : [doExeMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080003000 o: 'h0000000080003000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000020001001 o: 'h0000000020001001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003000 o: 'h0000000080003000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h06, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, shiftBEData: <V True True True True True True True True False False False False False False False False  > }, spec_bits: 'h000 }
+instret:11  PC:0x1ffff0000000000000000000080000018  instr:0x0012e293   iType:Alu    [doCommitNormalInst [0]]       1171
+instret:12  PC:0x1ffff000000000000000000008000001c  instr:0x00003317   iType:Auipc    [doCommitNormalInst [1]]       1171
+[RFile] wr_          1: r 50 <= 0000000020001400000000001fffff44000000
+               11720 : [doFinishMem] DTlbResp { resp: <'h0000000080003000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, vaddr: v: True a: 'h0000000080003000 o: 'h0000000080003000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003000, check_high: 'h00000000080003008, check_inclusive: True } }, specBits: 'h000 }
+outside TLB
+instret:13  PC:0x1ffff0000000000000000000080000020  instr:0xfe430313   iType:Alu    [doCommitNormalInst [0]]       1172
+[RFile] wr_          0: r 51 <= 0000000000020001400000001fffff44000000
+[RFile] wr_          1: r 54 <= 000000002000100f000000001fffff44000000
+instret:14  PC:0x1ffff0000000000000000000080000024  instr:0x00533023   iType:St    [doCommitNormalInst [0]]       1173
+instret:15  PC:0x1ffff0000000000000000000080000028  instr:0x00005297   iType:Auipc    [doCommitNormalInst [1]]       1173
+[RFile] wr_          1: r 52 <= 0000000008000500000000001fffff44000000
+[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003000, isMMIO: False, shiftedBE: <V True True True True True True True True False False False False False False False False  >, stData: TaggedData { tag: False, data: <V 'h0000000020001001 'h0000000000000000  > }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8024 }
+               11740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080003000, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8024 }
+instret:16  PC:0x1ffff000000000000000000008000002c  instr:0xfd828293   iType:Alu    [doCommitNormalInst [0]]       1174
+instret:17  PC:0x1ffff0000000000000000000080000030  instr:0x00c2d293   iType:Alu    [doCommitNormalInst [1]]       1174
+[RFile] wr_          0: r 53 <= 0000000008000500400000001fffff44000000
+               11750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other:  }, line: CLine { tag: <V False True False True  >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  >  > } }, repInfo: , setAuxData: tagged Invalid  }
+               11750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080003000, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8024 }
+               11750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace
+instret:18  PC:0x1ffff0000000000000000000080000034  instr:0x00a29293   iType:Alu    [doCommitNormalInst [0]]       1175
+instret:19  PC:0x1ffff0000000000000000000080000038  instr:0x0012e293   iType:Alu    [doCommitNormalInst [0]]       1176
+instret:20  PC:0x1ffff000000000000000000008000003c  instr:0x00004317   iType:Auipc    [doCommitNormalInst [1]]       1176
+               11770 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080003000, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8024 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080003000, fromState: I, toState: M, canUpToE: True, id: 'h0, child: , isPrefetchRq: False }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h06, rn2 'h04}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc4 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h06, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00005000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000004f }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+               12230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h06, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h06, rn2 'h06}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffb4 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h06, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
+               12240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h06, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffa8 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00003000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+[RFile] wr_          1: r 55 <= 0000000020001000000000001fffff44000000
+               12250 : [doExeMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080004000 o: 'h0000000080004000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000020001401 o: 'h0000000020001401 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080004000 o: 'h0000000080004000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h06, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, shiftBEData: <V True True True True True True True True False False False False False False False False  > }, spec_bits: 'h000 }
+               12250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h06, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffff }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Srl, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
+[RFile] wr_          0: r 58 <= 0000000020001413000000001fffff44000000
+[RFile] wr_          1: r 57 <= 0000000000000013c00000001fffff44000000
+               12260 : [doFinishMem] DTlbResp { resp: <'h0000000080004000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, vaddr: v: True a: 'h0000000080004000 o: 'h0000000080004000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080004000, check_high: 'h00000000080004008, check_inclusive: True } }, specBits: 'h000 }
+outside TLB
+               12260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h06, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
+instret:21  PC:0x1ffff0000000000000000000080000040  instr:0xfc430313   iType:Alu    [doCommitNormalInst [0]]       1226
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Or, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h06}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid  }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h06, rn2 'h06}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003f }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
+[RFile] wr_          0: r 59 <= 0000000020001400000000001fffff44000000
+               12270 : [doExeMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080005000 o: 'h0000000080005000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000004f o: 'h000000000000004f b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080005000 o: 'h0000000080005000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h06, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, shiftBEData: <V True True True True True True True True False False False False False False False False  > }, spec_bits: 'h000 }
+instret:22  PC:0x1ffff0000000000000000000080000044  instr:0x00533023   iType:St    [doCommitNormalInst [0]]       1227
+instret:23  PC:0x1ffff0000000000000000000080000048  instr:0x04f00293   iType:Alu    [doCommitNormalInst [1]]       1227
+[RFile] wr_          1: r 5b <= 0000000020000c16000000001fffff44000000
+               12280 : [doFinishMem] DTlbResp { resp: <'h0000000080005000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, vaddr: v: True a: 'h0000000080005000 o: 'h0000000080005000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080005000, check_high: 'h00000000080005008, check_inclusive: True } }, specBits: 'h000 }
+outside TLB
+instret:24  PC:0x1ffff000000000000000000008000004c  instr:0x00005317   iType:Auipc    [doCommitNormalInst [0]]       1228
+instret:25  PC:0x1ffff0000000000000000000080000050  instr:0xfb430313   iType:Alu    [doCommitNormalInst [1]]       1228
+[RFile] wr_          0: r 5c <= 0000000020000c00000000001fffff44000000
+instret:26  PC:0x1ffff0000000000000000000080000054  instr:0x00533023   iType:St    [doCommitNormalInst [0]]       1229
+instret:27  PC:0x1ffff0000000000000000000080000058  instr:0x00003297   iType:Auipc    [doCommitNormalInst [1]]       1229
+[RFile] wr_          0: r 5e <= 3fffffffffffffffcfff00001fffff44000000
+[RFile] wr_          1: r 5d <= 0000000000020000c00000001fffff44000000
+instret:28  PC:0x1ffff000000000000000000008000005c  instr:0xfa828293   iType:Alu    [doCommitNormalInst [0]]       1230
+[RFile] wr_          1: r 5f <= 2000000000000000080000001fffff44000000
+instret:29  PC:0x1ffff0000000000000000000080000060  instr:0x00c2d293   iType:Alu    [doCommitNormalInst [0]]       1231
+instret:30  PC:0x1ffff0000000000000000000080000064  instr:0xfff0031b   iType:Alu    [doCommitNormalInst [1]]       1231
+[RFile] wr_          0: r 60 <= 2000000000020000c80000001fffff44000000
+instret:31  PC:0x1ffff0000000000000000000080000068  instr:0x03f31313   iType:Alu    [doCommitNormalInst [0]]       1232
+instret:32  PC:0x1ffff000000000000000000008000006c  instr:0x0062e2b3   iType:Alu    [doCommitNormalInst [0]]       1233
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Csr, execFunc: tagged Alu Csrw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Valid csrAddrSATP, scr: tagged Invalid , imm: tagged Invalid  }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+               12490 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080003000, toState: M, child: , data: tagged Valid CLine { tag: <V False False False False  >, data: <V <V 'h0000000000000000 'h0000000000000000  > <V 'h0000000000000000 'h0000000000000000  > <V 'h0000000000000000 'h0000000000000000  > <V 'h0000000000000000 'h0000000000000000  >  > }, id: 'h0 }
+               12500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Valid 'h0, other:  }, line: CLine { tag: <V False False False False  >, data: <V <V 'h0000000000000000 'h0000000000000000  > <V 'h0000000000000000 'h0000000000000000  > <V 'h0000000000000000 'h0000000000000000  > <V 'h0000000000000000 'h0000000000000000  >  > } }, repInfo: , setAuxData: tagged Invalid  }
+               12500 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: 
+               12500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080003000, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8024 }
+[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: <V True True True True True True True True False False False False False False False False  >, shiftedData: TaggedData { tag: False, data: <V 'h0000000020001001 'h0000000000000000  > } }
+               12500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False False False False  >, data: <V <V 'h0000000020001001 'h0000000000000000  > <V 'h0000000000000000 'h0000000000000000  > <V 'h0000000000000000 'h0000000000000000  > <V 'h0000000000000000 'h0000000000000000  >  > } ; tagged Invalid 
+[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080004000, isMMIO: False, shiftedBE: <V True True True True True True True True False False False False False False False False  >, stData: TaggedData { tag: False, data: <V 'h0000000020001401 'h0000000000000000  > }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8044 }
+               12510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080004000, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 }
+               12520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other:  }, line: CLine { tag: <V False True False True  >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  >  > } }, repInfo: , setAuxData: tagged Invalid  }
+               12520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080004000, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 }
+               12520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace
+               12540 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080004000, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080004000, fromState: I, toState: M, canUpToE: True, id: 'h0, child: , isPrefetchRq: False }
+               13110 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080004000, toState: M, child: , data: tagged Valid CLine { tag: <V False False False False  >, data: <V <V 'h0000000000000000 'h0000000000000000  > <V 'h0000000000000000 'h0000000000000000  > <V 'h0000000000000000 'h0000000000000000  > <V 'h0000000000000000 'h0000000000000000  >  > }, id: 'h0 }
+               13120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040002, cs: M, dir: , owner: tagged Valid 'h1, other:  }, line: CLine { tag: <V False False False False  >, data: <V <V 'h0000000000000000 'h0000000000000000  > <V 'h0000000000000000 'h0000000000000000  > <V 'h0000000000000000 'h0000000000000000  > <V 'h0000000000000000 'h0000000000000000  >  > } }, repInfo: , setAuxData: tagged Invalid  }
+               13120 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: 
+               13120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080004000, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 }
+[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: <V True True True True True True True True False False False False False False False False  >, shiftedData: TaggedData { tag: False, data: <V 'h0000000020001401 'h0000000000000000  > } }
+               13120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False False False False  >, data: <V <V 'h0000000020001401 'h0000000000000000  > <V 'h0000000000000000 'h0000000000000000  > <V 'h0000000000000000 'h0000000000000000  > <V 'h0000000000000000 'h0000000000000000  >  > } ; tagged Invalid 
+[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080005000, isMMIO: False, shiftedBE: <V True True True True True True True True False False False False False False False False  >, stData: TaggedData { tag: False, data: <V 'h000000000000004f 'h0000000000000000  > }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8054 }
+               13130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080005000, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8054 }
+               13140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other:  }, line: CLine { tag: <V False True False True  >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  >  > } }, repInfo: , setAuxData: tagged Invalid  }
+               13140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080005000, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8054 }
+               13140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace
+               13160 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080005000, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8054 } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080005000, fromState: I, toState: M, canUpToE: True, id: 'h1, child: , isPrefetchRq: False }
+               13640 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080005000, toState: M, child: , data: tagged Valid CLine { tag: <V False False False False  >, data: <V <V 'h0000000000000000 'h0000000000000000  > <V 'h0000000000000000 'h0000000000000000  > <V 'h0000000000000000 'h0000000000000000  > <V 'h0000000000000000 'h0000000000000000  >  > }, id: 'h1 }
+               13650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040002, cs: M, dir: , owner: tagged Valid 'h2, other:  }, line: CLine { tag: <V False False False False  >, data: <V <V 'h0000000000000000 'h0000000000000000  > <V 'h0000000000000000 'h0000000000000000  > <V 'h0000000000000000 'h0000000000000000  > <V 'h0000000000000000 'h0000000000000000  >  > } }, repInfo: , setAuxData: tagged Invalid  }
+               13650 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: 
+               13650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080005000, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8054 }
+[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: <V True True True True True True True True False False False False False False False False  >, shiftedData: TaggedData { tag: False, data: <V 'h000000000000004f 'h0000000000000000  > } }
+               13650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False False False False  >, data: <V <V 'h000000000000004f 'h0000000000000000  > <V 'h0000000000000000 'h0000000000000000  > <V 'h0000000000000000 'h0000000000000000  > <V 'h0000000000000000 'h0000000000000000  >  > } ; tagged Invalid 
+instret:33  PC:0x1ffff0000000000000000000080000070  instr:0x18029073   iType:Csr    [doCommitSystemInst]       1366
+instret:34  PC:0x1ffff0000000000000000000080000074  instr:0x12000073   iType:SFence    [doCommitSystemInst]       1637
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h07, rn2 'h18}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff98 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00002000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1c, rn2 'h1c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffff8cd }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h65, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h66, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h09}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00449000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1c, rn2 'h1c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000455 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h68, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1c, rn2 'h1c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000e }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h66, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1c, rn2 'h1c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000667 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h69, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1c, rn2 'h1c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h68, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h69, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
+[RFile] wr_          1: r 63 <= 000000002000081e000000001fffff44000000
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1c, rn2 'h1c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000788 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h6b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1c, rn2 'h1c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h15, t: 'h2b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
+[RFile] wr_          0: r 64 <= 0000000020000804000000001fffff44000000
+[RFile] wr_          1: r 65 <= 0000000000112400000000001fffff44000000
+instret:35  PC:0x1ffff0000000000000000000080000078  instr:0x00002397   iType:Auipc    [doCommitNormalInst [0]]       1912
+  [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h07, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } }
+[RFile] wr_          0: r 66 <= 0000000000112233400000001fffff44000000
+instret:36  PC:0x1ffff000000000000000000008000007c  instr:0xf9838393   iType:Alu    [doCommitNormalInst [0]]       1913
+instret:37  PC:0x1ffff0000000000000000000080000080  instr:0x00449e37   iType:Alu    [doCommitNormalInst [1]]       1913
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Neq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1c, rn2 'h1d, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000014 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h054 }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h17, t: 'h2f }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h07, rn2 'h07, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+[RFile] wr_          1: r 67 <= 00000004488cd000000000001fffff44000000
+               19140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h07, rn2 'h07, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+instret:38  PC:0x1ffff0000000000000000000080000084  instr:0x8cde0e1b   iType:Alu    [doCommitNormalInst [0]]       1914
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff54 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h18, t: 'h31 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00002000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+[RFile] wr_          0: r 68 <= 00000004488cd115400000001fffff44000000
+               19150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h07, rn2 'h07, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
+instret:39  PC:0x1ffff0000000000000000000080000088  instr:0x00ee1e13   iType:Alu    [doCommitNormalInst [0]]       1915
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
+[RFile] wr_          1: r 69 <= 00004488cd115400000000001fffff44000000
+               19160 : [doExeMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080002010 o: 'h0000000080002010 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002010 o: 'h0000000080002010 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h07, rn2 'h07, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, shiftBEData: <V True True True True True True True True False False False False False False False False  > }, spec_bits: 'h000 }
+instret:40  PC:0x1ffff000000000000000000008000008c  instr:0x455e0e13   iType:Alu    [doCommitNormalInst [0]]       1916
+[RFile] wr_          0: r 6a <= 00004488cd115599c00000001fffff44000000
+               19170 : [doFinishMem] DTlbResp { resp: <'h0000000080002010,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, vaddr: v: True a: 'h0000000080002010 o: 'h0000000080002010 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002010, check_high: 'h00000000080002018, check_inclusive: True } }, specBits: 'h000 }
+outside TLB
+               19170 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080002010, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, pcHash: 'h80a4 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid  } ; tagged ToCache 
+               19170 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h07, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+               19170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080002010, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a4 }
+instret:41  PC:0x1ffff0000000000000000000080000090  instr:0x00ce1e13   iType:Alu    [doCommitNormalInst [0]]       1917
+[RFile] wr_          1: r 6b <= 04488cd115599c00011200001fffff44000000
+               19180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other:  }, line: CLine { tag: <V False True False True  >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  >  > } }, repInfo: , setAuxData: tagged Invalid  }
+               19180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080002010, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a4 }
+               19180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace
+               19180 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h6c, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h07, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
+               19180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+instret:42  PC:0x1ffff0000000000000000000080000094  instr:0x667e0e13   iType:Alu    [doCommitNormalInst [0]]       1918
+[RFile] wr_          0: r 6c <= 04488cd115599de2011200001fffff44000000
+[RFile] wr_          1: r 70 <= 000000002000082b000000001fffff44000000
+               19190 : [doExeMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080002010 o: 'h0000000080002010 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h1122334455667788 o: 'h1122334455667788 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002010 o: 'h0000000080002010 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h07, rn2 'h1c, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, shiftBEData: <V True True True True True True True True False False False False False False False False  > }, spec_bits: 'h000 }
+               19190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 }
+instret:43  PC:0x1ffff0000000000000000000080000098  instr:0x00ce1e13   iType:Alu    [doCommitNormalInst [0]]       1919
+               19200 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080002010, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a4 } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002010, fromState: I, toState: E, canUpToE: True, id: 'h1, child: , isPrefetchRq: False }
+[RFile] wr_          0: r 71 <= 0000000020000800000000001fffff44000000
+[RFile] wr_          1: r 72 <= 0000000000000000400000001fffff44000000
+               19200 : [doFinishMem] DTlbResp { resp: <'h0000000080002010,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, vaddr: v: True a: 'h0000000080002010 o: 'h0000000080002010 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002010, check_high: 'h00000000080002018, check_inclusive: True } }, specBits: 'h000 }
+outside TLB
+               19200 : [doExeMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, shiftBEData: <V True True True True True True True True False False False False False False False False  > }, spec_bits: 'h001 }
+instret:44  PC:0x1ffff000000000000000000008000009c  instr:0x788e0e13   iType:Alu    [doCommitNormalInst [0]]       1920
+               19210 : [doFinishMem] DTlbResp { resp: <'h0000000080002000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h19, t: 'h33 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, vaddr: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002000, check_high: 'h00000000080002008, check_inclusive: True } }, specBits: 'h001 }
+outside TLB
+instret:45  PC:0x1ffff00000000000000000000800000a0  instr:0x01c3b023   iType:St    [doCommitNormalInst [0]]       1921
+[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h16, t: 'h2d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080002010, isMMIO: False, shiftedBE: <V True True True True True True True True False False False False False False False False  >, stData: TaggedData { tag: False, data: <V 'h1122334455667788 'h0000000000000000  > }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80a0 }
+               19220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080002010, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 }
+               19230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other:  }, line: CLine { tag: <V False True False True  >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  >  > } }, repInfo: , setAuxData: tagged Invalid  }
+               19230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080002010, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 }
+               19230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h1a, t: 'h35 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h1b, t: 'h37 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h1c, t: 'h39 }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h1d, t: 'h3b }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h1e, t: 'h3d }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h1f, t: 'h3f }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h00b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h00b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+               19950 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002010, toState: E, child: , data: tagged Valid CLine { tag: <V False False False False  >, data: <V <V 'h0000000000000000 'h0000000000000000  > <V 'h0000000000000000 'h0000000000000000  > <V 'h0000000000000000 'h0000000000000000  > <V 'h0000000000000000 'h0000000000000000  >  > }, id: 'h1 }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h00b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+               19960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other:  }, line: CLine { tag: <V False False False False  >, data: <V <V 'h0000000000000000 'h0000000000000000  > <V 'h0000000000000000 'h0000000000000000  > <V 'h0000000000000000 'h0000000000000000  > <V 'h0000000000000000 'h0000000000000000  >  > } }, repInfo: , setAuxData: tagged Invalid  }
+               19960 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: 
+               19960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080002010, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a4 }
+               19960 : [Ld resp] 'h01; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000  > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }
+Performance count hit latency
+Performance monitoring hit
+               19960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False False False False  >, data: <V <V 'h0000000000000000 'h0000000000000000  > <V 'h0000000000000000 'h0000000000000000  > <V 'h0000000000000000 'h0000000000000000  > <V 'h0000000000000000 'h0000000000000000  >  > } ; tagged Valid 'h4
+               19970 : [doRespLdMem] 'h01; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000  > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000  > } }
+[RFile] wr_          3: r 6e <= 0000000000000000000000001fffff44000000
+               19970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other:  }, line: CLine { tag: <V False False False False  >, data: <V <V 'h0000000000000000 'h0000000000000000  > <V 'h0000000000000000 'h0000000000000000  > <V 'h0000000000000000 'h0000000000000000  > <V 'h0000000000000000 'h0000000000000000  >  > } }, repInfo: , setAuxData: tagged Invalid  }
+               19970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080002010, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 }
+               19970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit
+               19970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080002010, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 }
+[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: <V True True True True True True True True False False False False False False False False  >, shiftedData: TaggedData { tag: False, data: <V 'h1122334455667788 'h0000000000000000  > } }
+               19970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False False False False  >, data: <V <V 'h0000000000000000 'h0000000000000000  > <V 'h1122334455667788 'h0000000000000000  > <V 'h0000000000000000 'h0000000000000000  > <V 'h0000000000000000 'h0000000000000000  >  > } ; tagged Invalid 
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080002010, isMMIO: False, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, fault: tagged Invalid , allowCap: False, killed: tagged Valid St }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h00d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+[ALU redirect -           1] 'h1ffff00000000000000000000800000bc; 'h0; InstTag { way: 'h1, ptr: 'h17, t: 'h2f }
+[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h17, t: 'h2f } ; 'h0 ; 'h0 ; <V 'h09 'h09  > ; <V 'h17 'h17  > ; <V <V True True True True True True True True True False False False False False False False False False False False False False False True True True True True True True True True  > <V True True True True True True True True True False False False False False False False False False False False False False False True True True True True True True True True  >  > ; <V <V True True True True True True True True True False False False False False False False False False False False False False False False True True True True True True True True  > <V True True True True True True True True True False False False False False False False False False False False False False False False True True True True True True True True  >  > ; 'h0 ; <V 'h18 'h18  > ; <V 'h11 'h11  >
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Neq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1c, rn2 'h1d, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000014 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h800, localHist: 'h355, globalTaken: True, localTaken: False, pcIndex: 'h054 }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h6c, src2: tagged Valid 'h6e, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h07, rn2 'h07, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+               20100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h07, rn2 'h07, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+               20110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h07, rn2 'h07, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
+               20120 : [doExeMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080002010 o: 'h0000000080002010 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002010 o: 'h0000000080002010 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h07, rn2 'h07, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, shiftBEData: <V True True True True True True True True False False False False False False False False  > }, spec_bits: 'h000 }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00002000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff54 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
+               20130 : [doFinishMem] DTlbResp { resp: <'h0000000080002010,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, vaddr: v: True a: 'h0000000080002010 o: 'h0000000080002010 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002010, check_high: 'h00000000080002018, check_inclusive: True } }, specBits: 'h000 }
+outside TLB
+               20130 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080002010, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, pcHash: 'h80a4 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid  } ; tagged ToCache 
+               20130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080002010, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a4 }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h72, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
+               20140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Invalid , other:  }, line: CLine { tag: <V False False False False  >, data: <V <V 'h0000000000000000 'h0000000000000000  > <V 'h1122334455667788 'h0000000000000000  > <V 'h0000000000000000 'h0000000000000000  > <V 'h0000000000000000 'h0000000000000000  >  > } }, repInfo: , setAuxData: tagged Invalid  }
+               20140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080002010, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a4 }
+               20140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
+               20140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080002010, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a4 }
+               20140 : [Ld resp] 'h02; TaggedData { tag: False, data: <V 'h1122334455667788 'h0000000000000000  > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }
+Performance count hit latency
+Performance monitoring hit
+               20140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False False False False  >, data: <V <V 'h0000000000000000 'h0000000000000000  > <V 'h1122334455667788 'h0000000000000000  > <V 'h0000000000000000 'h0000000000000000  > <V 'h0000000000000000 'h0000000000000000  >  > } ; tagged Invalid 
+               20150 : [doRespLdMem] 'h02; TaggedData { tag: False, data: <V 'h1122334455667788 'h0000000000000000  > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'h1122334455667788 'h0000000000000000  > } }
+[RFile] wr_          3: r 6e <= 04488cd115599de2011200001fffff44000000
+               20150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+[RFile] wr_          0: r 70 <= 000000002000082b000000001fffff44000000
+[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False }, paddr: 'h0000000080002010, isMMIO: False, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, fault: tagged Invalid , allowCap: False, killed: tagged Invalid  }
+               20160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h71, src2: tagged Valid 'h72, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h001 }
+[RFile] wr_          0: r 72 <= 0000000000000000400000001fffff44000000
+[RFile] wr_          1: r 71 <= 0000000020000800000000001fffff44000000
+               20170 : [doExeMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, shiftBEData: <V True True True True True True True True False False False False False False False False  > }, spec_bits: 'h001 }
+instret:46  PC:0x1ffff00000000000000000000800000a4  instr:0x0003be83   iType:Ld    [doCommitNormalInst [0]]       2017
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+               20180 : [doFinishMem] DTlbResp { resp: <'h0000000080002000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, vaddr: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002000, check_high: 'h00000000080002008, check_inclusive: True } }, specBits: 'h001 }
+outside TLB
+instret:47  PC:0x1ffff00000000000000000000800000a8  instr:0x01de1a63   iType:Br    [doCommitNormalInst [0]]       2019
+instret:48  PC:0x1ffff00000000000000000000800000ac  instr:0x00002297   iType:Auipc    [doCommitNormalInst [1]]       2019
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+instret:49  PC:0x1ffff00000000000000000000800000b0  instr:0xf5428293   iType:Alu    [doCommitNormalInst [0]]       2020
+instret:50  PC:0x1ffff00000000000000000000800000b4  instr:0x00100313   iType:Alu    [doCommitNormalInst [1]]       2020
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h005, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+[doDeqStQ_MMIO_issue] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080002000, isMMIO: True, shiftedBE: <V True True True True True True True True False False False False False False False False  >, stData: TaggedData { tag: False, data: <V 'h0000000000000001 'h0000000000000000  > }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h80b8 }; MMIOCRq { addr: 'h0000000080002000, func: tagged St , byteEn: <V True True True True True True True True False False False False False False False False  >, data: TaggedData { tag: False, data: <V 'h0000000000000001 'h0000000000000000  > }, loadTags: False }
+counting performance
+1
+enters inside
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h006, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+2026: mmioPlatform.rl_tohost: 0x1 (= 1)
+PASS

builds/Resources/Include_Common.mk

@@ -56,6 +56,8 @@ BSC_COMPILATION_FLAGS += \
 	-D FABRIC64    \
 	-D BLUESIM \
 	-D PERFORMANCE_MONITORING \
+	-D PERF_COUNT \
+	-D STATCOUNTERS \
 	-keep-fires -aggressive-conditions -no-warn-action-shadowing -check-assert \
 	-suppress-warnings G0020 -steps-max-intervals 10000000   \
 	-steps-warn-interval 1000000 \
@@ -109,7 +111,7 @@ benchmarks:
 
 # ================================================================
 # Generate Bluespec CHERI tag controller source file
-CAPSIZE = 128 	
+CAPSIZE = 128
 TAGS_STRUCT = 0 64
 TAGS_ALIGN = 32
 .PHONY: tagsparams

builds/Resources/Include_RISCY_Config.mk

@@ -112,6 +112,7 @@ BSC_COMPILATION_FLAGS += \
 	-D RISCV \
 	-D TSO_MM \
 	-D RV64 \
+	-D PERF_COUNT \
 	-D ISA_PRIV_M  -D ISA_PRIV_S  -D ISA_PRIV_U  \
 	-D SV39 \
 	-D ISA_I  -D ISA_M  -D ISA_A  -D ISA_F  -D ISA_D  -D ISA_FD_DIV  -D ISA_C  \

src_Core/CPU/Core.bsv

@@ -366,6 +366,11 @@ module mkCore#(CoreId coreId)(Core);
         // whether perf data is collected
         Reg#(Bool) doStatsReg <- mkConfigReg(True);
 
+        // Hack to get set stat reg to true
+        // rule forceSetStatRegToTrue;
+        //     doStatsReg <= True;
+        // endrule
+
         // write aggressive elements + wakupe reservation stations
         function Action writeAggr(Integer wrAggrPort, PhyRIndx dst);
         action

src_Core/CPU/CsrFile.bsv

@@ -330,7 +330,8 @@ interface StatsCsr;
 endinterface
 
 module mkStatsCsr(StatsCsr);
-    Reg#(Bool) doStats <- mkConfigReg(False);
+    // Seeting CSR stat to true
+    Reg#(Bool) doStats <- mkConfigReg(True);
 
     FIFO#(Bool) writeQ <- mkFIFO1;
 

src_Core/ISA/ISA_Decls_CHERI.bsv

@@ -228,4 +228,4 @@ Bit #(3) f3_AMO_CAP = w_SIZE_CAP;
 Bit #(XLEN) otype_unsealed_ext = -1;
 Bit #(XLEN) otype_sentry_ext = -2;
 Bit #(XLEN) otype_res0_ext = -3;
-Bit #(XLEN) otype_res1_ext = -4;
+Bit #(XLEN) otype_res1_ext = -4;

src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv

@@ -320,7 +320,6 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
     // pipeline fifos
     let dispToRegQ <- mkMemDispToRegFifo;
     let regToExeQ <- mkMemRegToExeFifo;
-    // let trollToExeQ <- mkMemRegToExeFifo;
 
     // wire to recv bypass
     Vector#(TMul#(2, AluExeNum), RWire#(Tuple2#(PhyRIndx, CapPipe))) bypassWire <- replicateM(mkRWire);
@@ -531,14 +530,7 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
         if(x.regs.src1 matches tagged Valid .src1 &&& src1 != 0) begin
             rVal1 <- readRFBypass(src1, regsReady.src1, inIfc.rf_rd1(src1), bypassWire);
         end
-        if (x.ddc_offset) begin
-            $display("calling set address");
-            rVal1 = setAddr(ddc, getAddr(rVal1)).value;
-        end
-        else begin
-            $display("no called set address");
-        end
-        $display("outside if and else");
+        if (x.ddc_offset) rVal1 = setAddr(ddc, getAddr(rVal1)).value;
 
         // get rVal2 (check bypass)
         CapPipe rVal2 = nullCap;
@@ -605,12 +597,9 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
     endrule
 
     rule doExeMem;
-        $display("do exe");
         regToExeQ.deq;
         let regToExe = regToExeQ.first;
         let x = regToExe.data;
-        // trollToExeQ.enq(regToExe);
-        // ==============================
         if(verbose) $display("%t : [doExeMem] ", $time, fshow(regToExe));
 
         let shiftBE = DataMemAccess(x.shiftBEData);
@@ -658,19 +647,10 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
     endrule
 
     rule doFinishMem;
-        $display("do finish mem");
-        // trollToExeQ.deq;
-        // let regToExe = trollToExeQ.first;
-        // let lol = regToExe.data;
-        // =============================
         dTlb.deqProcResp;
         let dTlbResp = dTlb.procResp;
-        let x = dTlbResp.inst;  
+        let x = dTlbResp.inst;
         let {paddr, expCause, allowCapPTE} = dTlbResp.resp;
-        // paddr = getAddr(lol.vaddr);
-        // expCause = False;
-        // allowCapPTE = True;
-
         Maybe#(Trap) cause = Invalid;
         if (expCause matches tagged Valid .c) cause = Valid(Exception(c));
 
@@ -774,11 +754,6 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
         $display("KONATAS\t%0d\t%0d\t0\tMem4", cur_cycle, x.u_id);
         $fflush;
 `endif
-        // Try me! 
-        // if (x.mem_func == St) begin
-        //       paddr = 256;
-        // end
-
         // update LSQ
         LSQUpdateAddrResult updRes <- lsq.updateAddr(
             x.ldstq_tag, cause, x.allowCapLoad && allowCapPTE, paddr, isMMIO, x.shiftedBE
@@ -1492,6 +1467,7 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
         // MMIO may cause exception, must have spec tag, and only can be St/Amo
         doAssert(lsqDeqSt.memFunc == St || lsqDeqSt.memFunc == Amo, "must be St/Amo");
 `ifdef PERF_COUNT
+        $display(inIfc.doStats);
         if(inIfc.doStats) begin
             if(lsqDeqSt.acq) begin
                 exeLrScAmoAcqCnt.incr(1);

src_Core/RISCY_OOO/procs/lib/DTlb.bsv

@@ -144,7 +144,7 @@ typedef union tagged {
 module mkDTlb#(
     function TlbReq getTlbReq(instT inst)
 )(DTlb::DTlb#(instT)) provisos(Bits#(instT, a__));
-    Bool verbose = True;
+    Bool verbose = False;
 
     // TLB array
     DTlbArray tlb <- mkDTlbArray;
@@ -562,7 +562,6 @@ module mkDTlb#(
             // bare mode
             pendWait[idx] <= None;
             pendResp[idx] <= tuple3(r.addr, Invalid, True);
-            $display("bare mode");
             if(verbose) $display("DTLB %m req (bare): ", fshow(r));
         end
 

src_Core/RISCY_OOO/procs/lib/Decode.bsv

@@ -1003,7 +1003,6 @@ function DecodeResult decode(Instruction inst, Bool cap_mode);
                             regs.src1 = Valid(tagged Gpr rs1);
                             regs.src2 = Valid(tagged Gpr rs2);
                             dInst.capFunc = CapModify (SetBounds (SetBoundsRounding));
-                            // TODOD Add the delta function under this
                         end
                         f7_cap_CSetBoundsExact: begin
                             legalInst = True;

src_Core/RISCY_OOO/procs/lib/Exec.bsv

@@ -218,18 +218,7 @@ function CapPipe specialRWALU(CapPipe cap, CapPipe oldCap, SpecialRWFunc scrType
     return res;
 endfunction
 
-function Tuple2#(Data, Bool) extractType(CapPipe a) 
-    provisos (
-       CHERICap::CHERICap#(
-           CHERICC_Fat::CapPipe,   // capT
-           OTypeW,                 // otypeW
-           FlagsW,                 // flgW
-           CapAddrW,               // addrW
-           CapW,                   // inMemW
-           TSub#(MW,3),            // maskableW
-           Delta                   // delta
-       )
-   );
+function Tuple2#(Data, Bool) extractType(CapPipe a);
     if      (getKind(a) == UNSEALED) return tuple2(otype_unsealed_ext, True);
     else if (getKind(a) == SENTRY  ) return tuple2(otype_sentry_ext, True);
     else if (getKind(a) == RES0    ) return tuple2(otype_res0_ext, True);
@@ -252,7 +241,6 @@ function CapPipe capModify(CapPipe a, CapPipe b, CapModifyFunc func);
     new_hard_perms.global = new_hard_perms.global && getHardPerms(b).global;
     Bool unsealIllegal = !isValidCap(b) || getKind(b) != UNSEALED || getKind(a) == UNSEALED || a_res || getAddr(b) != a_type || !getHardPerms(b).permitUnseal || !isInBounds(b, False);
     Bool buildCapIllegal = !isValidCap(b) || getKind(b) != UNSEALED || !isDerivable(a) || (getPerms(a) & getPerms(b)) != getPerms(a) || getBase(a) < getBase(b) || getTop(a) > getTop(b); // XXX needs optimisation
-    // TODO: Delta handler function 
     CapPipe res = (case(func) matches
             tagged ModifyOffset .offsetOp :
                 modifyOffset(a_mut, getAddr(b), offsetOp == IncOffset).value;
@@ -285,9 +273,7 @@ function CapPipe capModify(CapPipe a, CapPipe b, CapModifyFunc func);
             tagged FromPtr                :
                 (getAddr(a) == 0 ? nullCap : setAddr(b_mut, getAddr(a)).value);
             tagged SetHigh:
-                //fromMem(tuple2(False, {getAddr(b), getAddr(a)}));
-                capFromAddrs(a,b);
-                // getTruncatedTuple(getAddr(b))
+                fromMem(tuple2(False, {getAddr(b), getAddr(a)}));
             tagged BuildCap               :
                 setKind(setValidCap(a_mut, !buildCapIllegal), getKind(a)==SENTRY ? SENTRY : UNSEALED);
             tagged Move                   :
@@ -299,39 +285,6 @@ function CapPipe capModify(CapPipe a, CapPipe b, CapModifyFunc func);
     return res;
 endfunction
 
-// function CapPipe capFromAddrs (CapPipe a, CapPipe b)
-// provisos (
-//     CHERICap#(CapPipe, o, f, addrW, CapW, m, d)
-// );
-
-//     // Get full serialized capability of 'a'
-//     match {.tag, .rawA} = toMem(a);   // rawA : Bit#(inMemW)
-
-//     // Replace low addrW bits with address from b
-//     Bit#(addrW) newAddr = getAddr(b);
-
-//     Bit#(inMemW) newRaw =
-//         { rawA[CapW-1 : addrW]   // keep upper metadata
-//         , newAddr                  // replace address field
-//         };
-
-//     return fromMem(tuple2(tag, newRaw));
-
-// endfunction
-function CapPipe capFromAddrs(capT a, capT b)
-    provisos (CHERICap#(capT, a, b, 64, d, e, f)); // exact instance
-    // Extract addresses
-    Bit#(64) addrA = getAddr(a);
-    Bit#(64) addrB = getAddr(b);
-    // Extra bits to reach inMemW = 180
-    Bit#(52) extra  = 0; // can be zeros or delta bits if needed
-
-    // Concatenate explicitly typed
-    Bit#(180) rawBits = {addrB, addrA, extra};
-
-    return fromMem(tuple2(False, rawBits));
-endfunction
-
 (* noinline *)
 function Data capInspect(CapPipe a, CapPipe b, CapInspectFunc func);
     Data res = (case(func) matches
@@ -370,17 +323,6 @@ function Data capInspect(CapPipe a, CapPipe b, CapInspectFunc func);
     return res;
 endfunction
 
-// function CapPipe getTruncatedTuple(AddrType a, AddrType b)
-//     provisos (
-//         Add#(a__, b__, 180) // Defines that a__ + b__ must equal 180
-//     );
-
-//     // Use a list literal or a Tuple constructor
-//     let address_bits = { getAddr(b), getAddr(a) };
-    
-//     return fromMem(tuple2(False, address_bits));
-// endfunction
-
 function CapPipe capALU(CapPipe a, CapPipe b, CapFunc func);
     CapPipe res = (case (func) matches
         tagged CapInspect .x:

src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv

@@ -310,7 +310,7 @@ typedef enum {
 } ModifyOffsetFunc deriving(Bits, Eq, FShow);
 
 typedef enum {
-    SetBoundsExact, SetBoundsRounding, CRRL, CRAM, SetDelta
+    SetBoundsExact, SetBoundsRounding, CRRL, CRAM
 } SetBoundsFunc deriving(Bits, Eq, FShow);
 
 typedef enum {
@@ -336,8 +336,6 @@ typedef enum {
 typedef union tagged {
     ModifyOffsetFunc ModifyOffset;
     SetBoundsFunc SetBounds;
-    // TODOD: Delta add type here
-    // SetDeltaFunc  SetDelta;
     SpecialRWFunc SpecialRW;
     AddrSource SetAddr;
     void Seal;
@@ -1070,7 +1068,7 @@ function Fmt showInst(Instruction inst);
   return ret;
 endfunction
 
-function x addPc(x cap, Bit#(12) inc) provisos (Add#(f, 12, c), CHERICap::CHERICap#(x, a, b, c, d, e, f)) = setAddrUnsafe(cap, getAddr(cap) + signExtend(inc));
+function x addPc(x cap, Bit#(12) inc) provisos (Add#(f, 12, c), CHERICap::CHERICap#(x, a, b, c, d, e)) = setAddrUnsafe(cap, getAddr(cap) + signExtend(inc));
 
 `ifdef PERFORMANCE_MONITORING
 typedef   8 Report_Width;

src_Core/RISCY_OOO/procs/lib/Types.bsv

@@ -49,11 +49,6 @@ import RVFI_DII_Types::*;
 typedef 64 AddrSz;
 typedef Bit#(AddrSz) Addr;
 
-// typedef struct {
-//     Vector#(2, Data) data;
-//     Bit#(52)         padding;
-// } MemData deriving (Bits);
-
 typedef 64 DataSz;
 typedef Bit#(DataSz) Data;
 typedef TDiv#(DataSz, 8) DataBytes;
@@ -65,7 +60,6 @@ typedef struct {
 function tag_t getTag(TaggedData#(tag_t, data_t) td) = td.tag;
 function data_t getData(TaggedData#(tag_t, data_t) td) = td.data;
 typedef Vector#(2, Data) MemData;
-// typedef Bit#(180) MemData;
 typedef Bool MemTag;
 typedef SizeOf#(MemData) MemDataSz;
 typedef TDiv#(MemDataSz, 8) MemDataBytes;

test.txt

@@ -0,0 +1,12 @@
+Let me know if this message works well on behalf of all of us.
+
+Hi Jan,
+This is a very small gesture from Jose, Mathews, Yukang and Akilan. We have transferred 200 pounds equally contributed by all of us. As you are moving in and settling into your new place, we hope this can help you and Samantha cover certain expenses like buying furniture or for your very efficient interrail travel pass in the near future.
+
+We will definetely miss the german embassy in Slatefort. Happy new year in advance from all of us!
+
+Regards,
+Jose, Mathews, Yukang and Akilan
+(Your UK representation of transportation
+reform)
+