120 lines
4.1 KiB
Verilog
120 lines
4.1 KiB
Verilog
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// Copyright (c) 2000-2009 Bluespec, Inc.
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to deal
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// in the Software without restriction, including without limitation the rights
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// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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// copies of the Software, and to permit persons to whom the Software is
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// furnished to do so, subject to the following conditions:
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// The above copyright notice and this permission notice shall be included in
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// all copies or substantial portions of the Software.
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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// THE SOFTWARE.
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//
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// $Revision: 24080 $
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// $Date: 2011-05-18 15:32:52 -0400 (Wed, 18 May 2011) $
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`ifdef BSV_WARN_REGFILE_ADDR_RANGE
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`else
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`define BSV_WARN_REGFILE_ADDR_RANGE 0
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`endif
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`ifdef BSV_ASSIGNMENT_DELAY
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`else
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`define BSV_ASSIGNMENT_DELAY
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`endif
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// Multi-ported Register File -- initializable from a file.
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module RegFileLoad(CLK,
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ADDR_IN, D_IN, WE,
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ADDR_1, D_OUT_1,
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ADDR_2, D_OUT_2,
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ADDR_3, D_OUT_3,
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ADDR_4, D_OUT_4,
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ADDR_5, D_OUT_5
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);
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parameter file = "";
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parameter addr_width = 1;
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parameter data_width = 1;
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parameter lo = 0;
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parameter hi = 1;
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parameter binary = 0;
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input CLK;
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input [addr_width - 1 : 0] ADDR_IN;
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input [data_width - 1 : 0] D_IN;
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input WE;
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input [addr_width - 1 : 0] ADDR_1;
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output [data_width - 1 : 0] D_OUT_1;
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input [addr_width - 1 : 0] ADDR_2;
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output [data_width - 1 : 0] D_OUT_2;
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input [addr_width - 1 : 0] ADDR_3;
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output [data_width - 1 : 0] D_OUT_3;
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input [addr_width - 1 : 0] ADDR_4;
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output [data_width - 1 : 0] D_OUT_4;
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input [addr_width - 1 : 0] ADDR_5;
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output [data_width - 1 : 0] D_OUT_5;
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reg [data_width - 1 : 0] arr[lo:hi];
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initial
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begin : init_rom_block
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if (binary)
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$readmemb(file, arr, lo, hi);
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else
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$readmemh(file, arr, lo, hi);
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end // initial begin
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always@(posedge CLK)
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begin
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if (WE)
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arr[ADDR_IN] <= `BSV_ASSIGNMENT_DELAY D_IN;
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end // always@ (posedge CLK)
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assign D_OUT_1 = arr[ADDR_1];
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assign D_OUT_2 = arr[ADDR_2];
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assign D_OUT_3 = arr[ADDR_3];
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assign D_OUT_4 = arr[ADDR_4];
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assign D_OUT_5 = arr[ADDR_5];
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// synopsys translate_off
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always@(posedge CLK)
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begin : runtime_check
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reg enable_check;
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enable_check = `BSV_WARN_REGFILE_ADDR_RANGE ;
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if ( enable_check )
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begin
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if (( ADDR_1 < lo ) || (ADDR_1 > hi) )
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$display( "Warning: RegFile: %m -- Address port 1 is out of bounds: %h", ADDR_1 ) ;
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if (( ADDR_2 < lo ) || (ADDR_2 > hi) )
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$display( "Warning: RegFile: %m -- Address port 2 is out of bounds: %h", ADDR_2 ) ;
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if (( ADDR_3 < lo ) || (ADDR_3 > hi) )
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$display( "Warning: RegFile: %m -- Address port 3 is out of bounds: %h", ADDR_3 ) ;
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if (( ADDR_4 < lo ) || (ADDR_4 > hi) )
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$display( "Warning: RegFile: %m -- Address port 4 is out of bounds: %h", ADDR_4 ) ;
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if (( ADDR_5 < lo ) || (ADDR_5 > hi) )
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$display( "Warning: RegFile: %m -- Address port 5 is out of bounds: %h", ADDR_5 ) ;
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if ( WE && ( ADDR_IN < lo ) || (ADDR_IN > hi) )
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$display( "Warning: RegFile: %m -- Write Address port is out of bounds: %h", ADDR_IN ) ;
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end
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end
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// synopsys translate_on
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endmodule
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