Akilan 6dcad25669 hardare implementation ready for testing

2026-03-18 12:41:06 +00:00

..

BSV_Additional_Libs

CreditCounter.bsv: Actually rate-limit

2020-07-06 15:59:47 +01:00

Core

test traces and log file for TLB check

2025-12-23 09:34:06 +00:00

CPU

hardare implementation ready for testing

2026-03-18 12:41:06 +00:00

Debug_Module

Fix debug module reset state machine

2024-09-16 23:15:24 +01:00

ISA

Fix Toooba to use addresses instead of offsets (#32)

2025-02-05 11:06:07 +00:00

PLIC

Changes to build with a 512-bit main data bus (with all other busses

2022-11-11 17:52:32 +00:00

RISCY_OOO

enabled performance counter in CSR register

2026-03-18 11:49:19 +00:00