rsnikhil db114186af More progress towards Tandem Verification trace generation (detail below) ...

Now handling all Alu and Fpu pipeline outputs, traps and xRets.
Still todo:
 (1) Mem pipeline outputs (Ld, Lr/Sc, Amo outputs to dest reg)
 (2) For CSRRx, currently reporting WARL pre-write updates; needs to be WARL'd update.

2020-02-10 15:08:08 -05:00

..

CoreW_IFC.bsv

Fixed up logic for "Non-Debug-Module reset" request/response from the Debug Module

2020-02-04 16:02:53 -05:00

CoreW.bsv

Minor tweaks, mostly cosmetic and $displays

2020-02-06 14:18:16 -05:00

Fabric_Defs.bsv

Initial load of files

2019-03-26 14:49:40 -04:00

Trace_Data2_to_Trace_Data.bsv

More progress towards Tandem Verification trace generation (detail below)

2020-02-10 15:08:08 -05:00

Trace_Data2.bsv

More progress towards Tandem Verification trace generation (detail below)

2020-02-10 15:08:08 -05:00

TV_Encode.bsv

Set verbosity to 0 in TV_Encode and Trace_Data2_to_Trace_Data

2020-01-30 13:39:54 -05:00

TV_Taps.bsv

Added support for 'debug_external_interrupt_req'

2019-04-01 12:26:54 -04:00