Jonathan Woodruff eee5a2c23b Experiment with a zero-cycle TLB in instruction fetch as well.

2024-01-16 10:05:17 +00:00

..

BSV_Additional_Libs

CreditCounter.bsv: Actually rate-limit

2020-07-06 15:59:47 +01:00

Core

Added missing DefaultValue import

2023-05-17 17:50:05 +01:00

CPU

Add a mean to configure starting PC dynamically at start of simulation

2023-07-13 15:34:08 +01:00

Debug_Module

Bump BlueStuff + use _Periph versions of parameters where needed

2022-11-18 12:07:24 +00:00

ISA

Cleanup unused exception code

2023-06-20 16:46:39 +01:00

PLIC

Changes to build with a 512-bit main data bus (with all other busses

2022-11-11 17:52:32 +00:00

RISCY_OOO

Experiment with a zero-cycle TLB in instruction fetch as well.

2024-01-16 10:05:17 +00:00