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Toooba/src_SSITH_P3/src_BSV
Jonathan Woodruff f86ea0203d Potential workaround for issue with vcu118 memory bus error.
Just use the same ID for all outstanding requests such that all requests
are in-order.
Previously we were working fine with requests serialised; requests
are now fully pipelined and out-of-order.
This change should roll back to in-order, but still pipelined.
This only affects the top-level used in the GFE (vcu118).
This design is working on the DE10 setup, so the issue is not
believed fundamental with CoreW.
2024-04-04 14:09:16 +01:00
..
2023-07-15 22:37:45 +01:00