Cheri-research/cheri-cap-lib
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Author SHA1 Message Date
Akilan
b772286261 saving current changes
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2026-02-23 11:44:35 +00:00
Akilan
f7884bb932 hack changes
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2026-02-20 01:59:12 +00:00
Akilan
bd95a8b5b1 saving current changes cheri-cap-lib
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2026-02-19 18:07:45 +00:00
Akilan
ed366654f0 saved compile time errors
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2026-02-17 15:34:56 +00:00
Akilan
b8f7b51e8a added latest changes 2026-02-17 14:49:00 +00:00
Akilan
76d832bcaf merge conflict resovled
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2026-02-17 14:26:25 +00:00
Akilan
b7892c3abc added changes 2026-02-17 14:22:33 +00:00
Akilan
dc9fc2bd7d added delta value field 2026-02-17 13:49:05 +00:00
Jonathan Woodruff
1d2c0b953b Add a property that setBounds will only return a valid cap if the bounds are within the original bounds.
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2025-03-07 15:12:46 +00:00
Peter Rugg
199e3c9f7f Extend forallCap to include almightyCap 2025-03-04 14:49:41 +00:00
Peter Rugg
7c9559524b Increase bit-widths of assertion modules 
These were hardwired for RV64, but I'm assuming having too many
bits will not be a problem for RV32?
 2025-03-04 14:49:41 +00:00
Peter Rugg
bad0d9cdb6 Default to 128-bit caps 2025-03-04 14:49:41 +00:00
Peter Rugg
c5da2ebc5d Move to building untracked files in subdirectories to improve cleaning 2025-03-04 14:49:41 +00:00
Alexandre Joannou
595447fd62 fix property following getLength return type change in b3896e4e50 2025-02-10 17:44:09 +00:00
Alexandre Joannou
2295c3b8c0 Added addAddrUnsafe verilog wrapper 2025-02-05 12:28:19 +00:00
Jonathan Woodruff
b3896e4e50 Move getLength to address length (not address length + 1), as we're explicitly saturating in order to express as a normal address. 2025-02-04 16:31:01 +00:00
Alexandre Joannou
3926b793bf Added an env var to control bsc vdir flag 2025-02-04 12:22:21 +00:00
Alexandre Joannou
9e0636e6fc Added test workflow 2025-02-04 11:10:09 +00:00
Jonathan Woodruff
033135b5f6 Add a new property that encoding and decoding a memory capability gives the same result. This caught the most recent bug. 2025-01-31 11:06:29 +00:00
Alexandre Joannou
eb6f9ebade Added setAddrUnsafe to generated verilog wrappers 2025-01-27 19:45:55 +00:00
Alexandre Joannou
0ca39912ba Let CapWrap build with CapMem and CapReg as well as CapPipe 2025-01-27 14:42:41 +00:00
Alexandre Joannou
19d3983010 Added an option to control the capability type used for verilog wrappers 2025-01-27 12:13:19 +00:00
Jonathan Woodruff
7212f50b4d Take into account tag clearing in setBounds. 2025-01-24 17:24:47 +00:00
Jonathan Woodruff
c2fe9cc093 Add rule in makefile to perform the formal property checks. 2025-01-24 15:20:14 +00:00
Matthew Naylor
d9e2fb788a Some properties that pass through SymbiYosys 2025-01-24 13:37:49 +00:00
PeterRugg
b29845fd65 Fix readme python-requirements typo 
Spotted by @jonwoodruff
 2025-01-10 16:58:15 +00:00
Marvel Renju
354a67386e Fix setBounds not clearing tag (#12) 
Ensure tag is cleared if the result is not in bounds
 2024-09-09 12:45:12 +01:00
Yuecheng Wang
7d229ec7d5 added isDerivable to verilog wrapper 2024-09-02 13:42:51 +01:00
Ivan Ribeiro
93a22d303d Merge pull request #11 from ivanmgribeiro/fusesoc 
Add FuseSoC support and a SystemVerilog wrapper generator
 2023-10-09 17:33:41 +01:00
Ivan Ribeiro
321c985fc8 Update fusesoc docs per version of OT repo used 
The previous documentation was using the python requirements from the
ibex repository rather than the OpenTitan repo.
 2023-10-08 14:06:04 +01:00
Ivan Ribeiro
f3284354d2 Remove "is" and "get" from generated SV fields 
This should make using the fields a little prettier
 2023-10-04 19:58:48 +01:00
Ivan Ribeiro
e4e1ed4c69 Add some documentation regarding FuseSoC 2023-10-02 18:14:36 +01:00
Ivan Ribeiro
ed0e4dfa65 Add capability size to name of modules and files 2023-10-02 17:46:29 +01:00
Ivan Ribeiro
a8898154d4 Add functions to CHERICapWrap.bsv 2023-10-02 17:46:29 +01:00
Ivan Ribeiro
06eff948d9 Fix bsv_src_root 
files_root is actually the directory where the fusesoc command was
executed, but what we want here is the location of the python file being
executed so we can find the bluespec sources
 2023-10-02 17:46:29 +01:00
Ivan Ribeiro
fd1f7c12a2 Add SystemVerilog wrappers to generator 2023-10-02 17:46:29 +01:00
Ivan Ribeiro
61e7b3e668 Add test core and targets 
To test, run:
fusesoc --cores-root . run --setup --target test ucam:cheri:cheri-cap-lib-test
 2023-10-02 17:46:29 +01:00
Ivan Ribeiro
fcadf1aead Add barebones fusesoc generator core 
This adds a fusesoc generator to create the verilog files from the
bluespec source.
 2023-10-02 17:46:29 +01:00
Ivan Ribeiro
a6664e512c Implement changes suggested by @gameboo + bugfix 
Uses argparse's "choices" argument, remove unused method and use abc and
for abstract methods.
Also updates the python filename in the Makefile
 2023-10-02 17:46:29 +01:00
Ivan Ribeiro
2d6864bbf3 New wrap script to support more languages (inc SV) 
At the moment, the original Blarney support is kept and support for a
SystemVerilog wrapper is added.
 2023-10-02 17:46:29 +01:00
Ivan Ribeiro
49de0f90f0 Reduce VA_Width to allow compilation 
This is almost certainly not the right fix but allows the code to
compile and the trim code is not used anywhere with CAP64
 2023-10-02 17:33:58 +01:00
Simon Moore
27e63bd9fd Remove HTML for adoc. 2023-08-30 18:38:32 +01:00
Jonathan Woodruff
cab12e0532 Add another couple missing exports. 2023-08-18 17:51:33 +00:00
Jonathan Woodruff
9dd923936f Add some missing exports. 2023-08-18 17:46:06 +00:00
Jonathan Woodruff
613af39b8f Add functions to compress/decompress the CapMem format where the tag is 
assumed to be set and the address is assumed to be a valid virtual
address.

This is being used for getting realistic area usage for the BTB.
 2023-08-18 17:33:25 +00:00
Peter Rugg
f11156ef9a Remove non-ascii characters 2023-01-25 16:27:06 +00:00
PeterRugg
7d9fdce16a Single cycle setBounds checking if the request is in bounds (#10) 2022-10-25 20:02:43 +01:00
Jonathan Woodruff
be80fbe51c Merge pull request #9 from CTSRD-CHERI/wip-aj443-bounds-info-api-refactor 
bounds info api refactor
 2022-10-25 10:43:07 +01:00
Alexandre Joannou
20daecce77 Update readme.adoc 2022-10-05 17:15:44 +01:00
Alexandre Joannou
6c71799edb Added a toc to CHERI_CAP_API 2022-09-30 17:30:04 +01:00