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Preserve name for verilog so component.xml doesn't have to be fixed.

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jon
2021-04-01 07:08:46 +01:00
parent 4b531fac46
commit 0701dea9a9
1 changed files with 3 additions and 4 deletions
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7
src_Core/RISCY_OOO/procs/lib/Btb.bsv
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@@ -85,13 +85,12 @@ typedef struct {
} VnD#(type data) deriving(Bits, Eq, FShow);
(* synthesize *)
module mkBtbSmall(NextAddrPred#(16));
NextAddrPred#(16) btb <- mkBtb;
module mkBtb(NextAddrPred#(16));
NextAddrPred#(16) btb <- mkBtbCore;
return btb;
endmodule
//(* synthesize *)
module mkBtb(NextAddrPred#(hashSz))
module mkBtbCore(NextAddrPred#(hashSz))
provisos (NumAlias#(tagSz, TSub#(TSub#(TSub#(AddrSz,SizeOf#(BtbBank)), SizeOf#(BtbIndex)), PcLsbsIgnore)),
Add#(1, a__, TDiv#(tagSz, hashSz)),
Add#(b__, tagSz, TMul#(TDiv#(tagSz, hashSz), hashSz)));