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FetchStage.bsv: Drop unused pc from Fetch3ToDecode

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Each instruction carries its own PC by this point, so it just duplicates
the PC of the first item in the vector. Moreover, when including a
pending straddle at the head, the PC value was not set to the previous
half's, ie PC-2. We keep pred_next_pc as that's used to determine where
the bundle is predicted to go next, and the duplication avoids having to
dynamically index the vector based on the number of instructions fed to
decode.
This commit is contained in:
Jessica Clarke
2020-04-08 04:22:49 +01:00
parent 85b4a738a9
commit 10c983d101
1 changed files with 0 additions and 3 deletions
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3
src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
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@@ -125,7 +125,6 @@ typedef struct {
} Fetch2ToFetch3 deriving(Bits, Eq, FShow);
typedef struct {
Addr pc;
Addr pred_next_pc;
Bool mispred_first_half;
Maybe#(Exception) cause;
@@ -692,7 +691,6 @@ module mkFetchStage(FetchStage);
if (pending_n_items == 0) begin
out = Fetch3ToDecode {
pc: fetch3In.pc,
pred_next_pc: pred_next_pc,
mispred_first_half: mispred_first_half,
cause: fetch3In.cause,
@@ -742,7 +740,6 @@ module mkFetchStage(FetchStage);
next_pending_n_items = truncate(n_items - fromInteger(valueOf(SupSize)));
rg_pending_decode <= drop(v_items);
rg_pending_f32d <= Fetch3ToDecode {
pc: v_items[valueOf(SupSize)].pc,
pred_next_pc: out.pred_next_pc,
mispred_first_half: False,
cause: tagged Invalid,