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Changed config to L1D Block-1 prefetcher and fixed potential bug

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This commit is contained in:
Karlis Susters
2023-02-28 12:29:38 +00:00
parent 7a352d774e
commit 6509cf6445
2 changed files with 4 additions and 4 deletions
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4
builds/Resources/Include_RISCY_Config.mk
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@@ -45,9 +45,9 @@ SIM_LLC_ARBITER_LAT ?=
# default check cache deadlock and rename error
CHECK_DEADLOCK ?= true
RENAME_DEBUG ?= false
INSTR_PREFETCHER_LOCATION ?= LL
INSTR_PREFETCHER_LOCATION ?= NONE
INSTR_PREFETCHER_TYPE ?= NEXT_LINE_ON_MISS
DATA_PREFETCHER_LOCATION ?= NONE
DATA_PREFETCHER_LOCATION ?= L1
DATA_PREFETCHER_TYPE ?= BLOCK
# clk frequency depends on core size

4
src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv
View File

@@ -959,12 +959,12 @@ module mkMarkovPrefetcher(Prefetcher) provisos
endmodule
module mkBlockPrefetcher(Prefetcher) provisos (
NumAlias#(numLinesEachWay, 2),
NumAlias#(numLinesEachWay, 1),
Alias#(lineCountT, Bit#(TLog#(TAdd#(numLinesEachWay, 1))))
);
Reg#(Bool) nextIsForward <- mkReg(?);
Reg#(LineAddr) prefetchAround <- mkReg(?);
Reg#(lineCountT) linesEachWayPrefetched <- mkReg(?);
Reg#(lineCountT) linesEachWayPrefetched <- mkReg(fromInteger(valueOf(numLinesEachWay)));
method Action reportAccess(Addr addr, HitOrMiss hitMiss);
if (hitMiss == MISS) begin
$display("%t Prefetcher report MISS %h", $time, addr);