Cheri-research/Toooba
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Insert deburster again on the vcu118-specific wrapper, as this design is known to work for the vcu118, or specifically, using the width converter.

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This commit is contained in:
Jonathan Woodruff
2024-04-05 14:06:42 +01:00
parent 854e8e5bfb
commit 70b82fb164
2 changed files with 8 additions and 4 deletions
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6
src_SSITH_P3/src_BSV/P3_Core.bsv
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@@ -177,8 +177,10 @@ module mkP3_Core (P3_Core_IFC);
, AXI4_Master #(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data_Periph, 0, 0, 0, 0, 0) )
wideS_narrowM <- mkAXI4DataWidthShim_WideToNarrow (proxyInDepth, proxyOutDepth);
match {.wideS, .narrowM} = wideS_narrowM;
let master0_inOrder <- mkAXI4SingleIDMaster(corew.manager_0);
mkConnection(master0_inOrder, wideS);
AXI4_Shim#(TAdd #(Wd_MId, 1), Wd_Addr, Wd_Data, 0, 0, 0, 0, 0)
manager_0_deburster <- mkBurstToNoBurst;
mkConnection(corew.manager_0, manager_0_deburster.slave);
mkConnection(manager_0_deburster.master, wideS);
// ================================================================
// Delay DRAM to compensate for relatively lower FPGA clock

6
src_Testbench/SoC/SoC_Top.bsv
View File

@@ -169,8 +169,10 @@ module mkSoC_Top #(Reset dm_power_on_reset)
, AXI4_Master #(TAdd#(Wd_MId,1), Wd_Addr, Wd_Data_Periph, 0, 0, 0, 0, 0) )
wideS_narrowM <- mkAXI4DataWidthShim_WideToNarrow (proxyInDepth, proxyOutDepth);
match {.wideS, .narrowM} = wideS_narrowM;
let master0_inOrder <- mkAXI4SingleIDMaster(corew.manager_0);
mkConnection(master0_inOrder, wideS);
AXI4_Shim#(TAdd #(Wd_MId, 1), Wd_Addr, Wd_Data, 0, 0, 0, 0, 0)
manager_0_deburster <- mkBurstToNoBurst;
mkConnection(corew.manager_0, manager_0_deburster.slave);
mkConnection(manager_0_deburster.master, wideS);
// SoC IPs
UART_IFC uart0 <- mkUART;