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Config for L1D Stride-4 prefetcher

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This commit is contained in:
Karlis Susters
2023-03-13 14:51:59 +00:00
parent 54b9f6669e
commit ada7d133e4
2 changed files with 2 additions and 2 deletions
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2
builds/Resources/Include_RISCY_Config.mk
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@@ -47,7 +47,7 @@ CHECK_DEADLOCK ?= true
RENAME_DEBUG ?= false
INSTR_PREFETCHER_LOCATION ?= NONE
INSTR_PREFETCHER_TYPE ?= SINGLE_WINDOW
DATA_PREFETCHER_LOCATION ?= L1LL
DATA_PREFETCHER_LOCATION ?= L1
DATA_PREFETCHER_TYPE ?= STRIDE
# clk frequency depends on core size

2
src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv
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@@ -1186,7 +1186,7 @@ endmodule
module mkBRAMStridePCPrefetcher(PCPrefetcher)
provisos(
NumAlias#(strideTableSize, 64),
NumAlias#(cLinesAheadToPrefetch, 3), // TODO fetch more if have repeatedly hit an entry, and if stride big
NumAlias#(cLinesAheadToPrefetch, 4), // TODO fetch more if have repeatedly hit an entry, and if stride big
Alias#(strideTableIndexT, Bit#(TLog#(strideTableSize)))
);
//Vector#(strideTableSize, Reg#(StrideEntry)) strideTable <- replicateM(mkReg(unpack(0)));