Config for L1D Stride-4 prefetcher

2023-03-13 14:51:59 +00:00
parent 54b9f6669e
commit ada7d133e4
2 changed files with 2 additions and 2 deletions
--- a/src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv
+++ b/src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv
@@ -1186,7 +1186,7 @@ endmodule
 module mkBRAMStridePCPrefetcher(PCPrefetcher)
 provisos(
    NumAlias#(strideTableSize, 64),
-    NumAlias#(cLinesAheadToPrefetch, 3), // TODO fetch more if have repeatedly hit an entry, and if stride big
+    NumAlias#(cLinesAheadToPrefetch, 4), // TODO fetch more if have repeatedly hit an entry, and if stride big
    Alias#(strideTableIndexT, Bit#(TLog#(strideTableSize)))
    );
    //Vector#(strideTableSize, Reg#(StrideEntry)) strideTable <- replicateM(mkReg(unpack(0)));