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Use forwarding BRAMs in L2 Cache. Duh; this is required for the new

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CCPipe structure.
This commit is contained in:
Jonathan Woodruff
2024-02-01 13:44:36 +00:00
parent 7608543da5
commit ccc71952bf
1 changed files with 2 additions and 2 deletions
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4
src_Core/RISCY_OOO/coherence/src/LLPipe.bsv
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@@ -162,9 +162,9 @@ module mkLLPipe(
Bool verbose = False;
// RAMs
Vector#(wayNum, RWBramCore#(indexT, infoT)) infoRam <- replicateM(mkRWBramCore);
Vector#(wayNum, RWBramCore#(indexT, infoT)) infoRam <- replicateM(mkRWBramCoreForwarded);
RWBramCore#(indexT, repT) repRam <- mkRandRepRam;
Vector#(wayNum, RWBramCore#(indexT, Line)) dataRam <- replicateM(mkRWBramCore);
Vector#(wayNum, RWBramCore#(indexT, Line)) dataRam <- replicateM(mkRWBramCoreForwarded);
// initialize RAM
Reg#(Bool) initDone <- mkReg(False);