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Merge branch 'CHERI' into jdw57-jr-bsc-safety

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Jonathan Woodruff
2021-10-08 09:50:45 +00:00
parent 520b09a6ed 3d0aee0af4
commit cec55419f5
3 changed files with 5 additions and 6 deletions
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4
src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv
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@@ -226,7 +226,7 @@ interface AluExePipeline;
endinterface
module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline);
Bool verbose = True;
Bool verbose = False;
Integer verbosity = 0;
// alu reservation station
@@ -323,7 +323,7 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline);
end
end
else if(x.dInst.iType == CJALR || x.dInst.iType == Jr) begin
let res_targets = inIfc.checkTarget(ppc);

2
src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv
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@@ -252,7 +252,7 @@ interface MemExePipeline;
endinterface
module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
Bool verbose = True;
Bool verbose = False;
// we change cache request in case of single core, becaues our MSI protocol
// is not good with single core

5
src_Core/RISCY_OOO/procs/lib/Fpu.bsv
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@@ -106,7 +106,7 @@ module mkDoubleSqrt(Server#(Tuple2#(Double, FpuRoundMode), Tuple2#(Double, FpuEx
`ifdef USE_XILINX_FPU
let fpu <- mkXilinxFpSqrt;
`else
let int_sqrt <- mkSquareRooter(1); // [sizhuo] size in RVFpu: 3
let int_sqrt <- mkNonPipelinedSquareRooter(3); // [sizhuo] size in RVFpu: 3
let fpu <- mkFloatingPointSquareRooter(int_sqrt);
`endif
return fpu;
@@ -344,7 +344,7 @@ function Tuple2#(Bit#(64), FpuException) float_to_int(
// necessary for rounding and overflow detection.
Bit#(TAdd#(66,m)) int_val = {64'b1, in.sfd, 2'b0}; // this is 2**m times larger than it should be - we will shift this to correct for that
int_val = saturating_shift_right(int_val, fromInteger(valueOf(m)) + bias_exp - in_exp);
// do rounding
// 00 : exact
// 01 : < 0.5
@@ -963,4 +963,3 @@ module mkFpuExecPipeline(FpuExec);
sqrtQ.specUpdate
));
endmodule