Add error clear implementation for delayShim

2023-07-12 15:34:12 +01:00
parent 23b471e0ae
commit d17d3135bb
1 changed files with 1 additions and 0 deletions
--- a/src_SSITH_P3/src_BSV/P3_Core.bsv
+++ b/src_SSITH_P3/src_BSV/P3_Core.bsv
@@ -137,6 +137,7 @@ module mkDelayShim #(Bit#(16) delay) (AXI4_Shim#(id_, addr_, data_, awuser_, wus
      interface ar = toSink(arff);
      interface r = toSource(rff);
   endinterface
+   interface clear = error("clear not supported");
 endmodule

 (* synthesize *)