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Don't write on CSpecialRW from R0

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This commit is contained in:
Peter Rugg
2020-05-11 23:52:04 +01:00
parent ec9f19dc26
commit f0bcd2ccd1
2 changed files with 2 additions and 2 deletions
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2
src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv
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@@ -332,7 +332,7 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline);
// The above case will never be valid due to assertions above, but the below one will be in the case of CJALR.
// This means that we will have instructions that both write SCR registers and also get mispredictions, unlike
// the CSR file. Given the assertions above, this seems dangerous...
scrData: isValid(x.dInst.scr) ? Valid (exec_result.scrData) : tagged Invalid,
scrData: isValid(x.dInst.scr) && x.dInst.iType == Scr ? Valid (exec_result.scrData) : tagged Invalid,
capException: exec_result.capException,
check: exec_result.boundsCheck,
`ifdef RVFI

2
src_Core/RISCY_OOO/procs/lib/Decode.bsv
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@@ -900,7 +900,7 @@ function DecodeResult decode(Instruction inst, Bool cap_mode);
f3_cap_ThreeOp: begin
case (funct7)
f7_cap_CSpecialRW: begin
dInst.iType = Scr;
dInst.iType = rs1 == 0 ? Cap : Scr;
regs.dst = Valid(tagged Gpr rd);
regs.src1 = Valid(tagged Gpr rs1);
regs.src2 = Invalid;