Commit Graph

11 Commits

Author SHA1 Message Date
Jessica Clarke
17ed2dfde8 Revert CACHE_SIZE back to LARGE
The default was erroneously changed, causing P3 builds to have smaller
caches, so switch it back. The RVFI-DII builds override this with a TEST
configuration anyway now.
2020-07-05 21:44:17 +01:00
Jessica Clarke
0b0b863baa Replace home-grown dependency script with Bluespec-provided makedepend.tcl
This one has the advantage of being able to be called with the same
flags as bsc, rather than needing to pass things through special
environment variables. As a result, revert all our changes to dealing
with BSC_COMPILATION_FLAGS (some of this diff therefore looks strangely
formatted, but it's to match upstream verbatim, and should be left that
way to minimise diffs and avoid conflicts).
2020-07-05 21:26:18 +01:00
jon
8ae5d3a1b2 Build RVFI_DII Toooba with very small caches, 2-way set associative to
maximise cache and memory verification.
2020-05-28 10:59:08 +01:00
Alexandre Joannou
370ed61bc4 Integrate the generation of dependenices to Makefiles 2020-04-23 14:55:28 +01:00
Jonathan Woodruff
3a79b022ea Merge branch 'master' into RVFI_DII, a complex merge for the fetch stage! 2020-03-18 11:35:59 +00:00
Jonathan Woodruff
909423e8e8 Use smaller L2 size (256KiB) for TestRIG. 2019-12-13 13:00:52 +00:00
Niraj Nayan Sharma
601bbe5a82 No longer using Xilinx FPU modules 2019-12-14 12:44:02 +05:30
rsnikhil
666dd2ad92 Small tweak to remove unnecessary explicit boot rom addrs (subsumed by IO) 2019-04-22 15:12:30 -04:00
rsnikhil
51bdff05d8 Updated Run_regression.py to utilize parallel processes 2019-04-18 18:42:06 -04:00
rsnikhil
47985fa93f Updated Makefiles so in src_SSITH_P3, RTL refers to Xilinx FP RTL instead of simulation models 2019-04-04 13:10:45 -04:00
rsnikhil
ee24a93944 Initial load of files 2019-03-26 14:49:40 -04:00