Cheri-research/Toooba
1
0
Fork 0
Code Issues 1 Pull Requests Actions Packages Projects Releases Wiki Activity
537 Commits 7 Branches 0 Tags
057964e94069a548d8da01ac7c0efced5fa84f60
Commit Graph

537 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Peter Rugg
057964e940 Some more tagsparam makefile fixes 2021-03-18 11:09:26 +00:00
Marno
e759077259 Made sure TagTableStructure.bsv is present upon regenration of .depends.mk 2021-03-18 10:47:15 +00:00
Marno
e7d0a6adf6 Removing TagTableStructure.bsv and .depends.mk on clean 2021-03-17 16:53:03 +00:00
Marno
df6cc12abb Removed TagTableStructure.bsv files from repo because these are now automatically generated 2021-03-17 16:01:16 +00:00
Marno
db57e909fc Added calling tagsparams.py in Include_Common.mk 2021-03-17 15:56:03 +00:00
Franz Fuchs
c5a0d38a63 Enabled HPM by default in builds/RV64ACDFIMSUxCHERI_Toooba_verilator/ 2021-03-16 13:19:47 +00:00
Peter Rugg
80fb97cc62 Take Bluestuff-ified Giraffe_IFC from Flute 2021-03-15 12:25:38 +00:00
Peter Rugg
395a9d1c02 Remove unused non-existent libraries from ssith Makefile 2021-03-15 11:26:24 +00:00
Jessica Clarke
d722d851d9 verilator_config.vlt: Hopefully suppress deprecation warnings for 4.026 2021-03-11 14:11:38 +00:00
jon
8de3cfffeb Remove debug print statements. 2021-03-10 17:03:35 +00:00
Jonathan Woodruff
6ef565e56c Fix bugs in previous commit due to test build not using performance 
counters.
 2021-03-09 16:05:01 +00:00
jon
1ef2d0cbeb Include both execute redirect and commit redirect in "redirect" counter. 2021-03-09 15:57:15 +00:00
Marno van der Maas
da1fd3781a Correction in testbench section 2021-03-09 10:58:56 +00:00
Marno van der Maas
f3f52d85ea Added links to RiscyOO and CHERI 2021-03-09 10:55:17 +00:00
Marno van der Maas
d3f40216a9 Made the unimplemented notation consistent 2021-03-09 10:46:55 +00:00
jon
fe7977e4e9 Fix typo when removing commented out code. 2021-03-06 07:24:49 +00:00
jon
8da520175f Use an (unguarded) BRAM in the Btb. 
Also, assume that a target that is not taken should be removed from the
Btb.  (The read that checked isn't possible with BRAM timing unless we
latched and had an extra port, but removing the check actually improved
performance a bit in CoreMark, and the pipeline should actually only be
reporting a non-taken branch if we did something wrong.)
 2021-03-06 07:19:50 +00:00
jon
4b411bf752 A Btb with 1/4 the storage that will (hopefully) infer as BRAM. 2021-03-05 12:14:26 +00:00
jon
7aea0325fc Add cycles to commit instruction reports to help with performance 
debugging.
 2021-03-05 12:12:33 +00:00
jon
89f0c3a45f Reduce verbosity. 2021-03-05 12:11:49 +00:00
Franz Fuchs
39e895ca4e added documentation of hardware performance monitoring events 
This document lists all implemented events and gives a short explanation
of what counting these events means.
 2021-03-04 16:45:02 +01:00
jon
6ea387f744 Fix performance bug in PC compression where we execute across a page 
boundary.
 2021-03-04 14:41:50 +00:00
Peter Rugg
0e1e2249a6 Default to dual-core builds 2021-03-04 11:54:35 +00:00
Jonathan Woodruff
db08e96596 Add Btb to the component.xml. 2021-03-03 20:27:31 +00:00
Peter Rugg
7a1d234e40 Merge branch 'ifetch-cleanup' into CHERI 2021-03-02 11:57:31 +00:00
Jessica Clarke
9dc27542f3 Use order-only prerequisites for directories 
Hopefully this stops .depends.mk from being generated more than
necessary, as presumably the fact that compile and simulator both add
new files to build_dir (and Verilog_RTL for Verilator) causes the
timestamp to change and thus make to think .depends.mk is stale.
 2021-02-28 04:14:54 +00:00
Jessica Clarke
e1060ac43d TlbTypes: Fix exception code reported for some store page fault conditions 
The mode and well-formedness checks above also set fault to True, so we
end up with cases where a DataStore request uses the default load page
fault exception code. Instead, unconditionally set excStorePageFault for
DataStore, and conditionally override to excStoreCapPageFault when
appropriate, being particularly careful to ensure earlier exception
causes still take precedence.

Also restructure the InstFetch and DataLoad cases to match how DataStore
needs to look.

This fixes the rv64si-p-dirty ISA test, currently the sole failure.
 2021-02-28 03:51:05 +00:00
Jessica Clarke
c7bd60b47e CSRs: Don't guard HPM CSRs with PERFORMANCE_MONITORING 
They always exist, just WARL so can be hard-wired.
 2021-02-28 01:11:39 +00:00
jon
9d5095b076 Count CJALRs with Jrs. 2021-02-24 20:36:46 +00:00
Jessica Clarke
df430e22c8 Exec: Enable non-ASR access to TIME 
This is needed for benchmarking.
 2021-02-24 04:17:42 +00:00
Jessica Clarke
7776bac8b5 Exec: Enable non-ASR access to HPMCOUNTERn 
These are now defined, and needed for benchmarking.
 2021-02-23 20:35:18 +00:00
Peter Rugg
5b6e8d88f6 Add CSetEqualExact 2021-02-22 17:44:36 +00:00
Peter Rugg
53eb073fb2 Don't track generated Verilog 2021-02-19 19:45:00 +00:00
jon
2f0b0c110f Use the necessary number of ports. 2021-02-19 17:38:16 +00:00
jon
b5bce1209a Revert "Revert biggest scheduling change from potentially problematic commit." 
This one does not actually build with the new BSC compiler.  I forgot to
test the hardware build (with GDB), which is where we have the problem.
This reverts commit b4308e9a6e.
 2021-02-19 17:38:16 +00:00
Peter Rugg
9f0968b1cb Fix AXI_Size=16 for MMIO of caps 2021-02-19 17:19:47 +00:00
Peter Rugg
47c94b5a34 Map more RAM in SSITH build 2021-02-19 09:25:41 +00:00
jon
b4308e9a6e Revert biggest scheduling change from potentially problematic commit. 
This still builds with the new BSC compile.
 2021-02-18 15:18:58 +00:00
jon
1fbf786294 Add to synthesis file set. 2021-02-17 21:26:54 +00:00
jon
eaf7a4ace7 Add one more missing file and clean up some duplicates. 2021-02-17 18:37:52 +00:00
jon
0f3fd15d41 Initial implementation of map of HPM counters into supervisor and user 
mode.  This version just unconditionally exposes them.
 2021-02-17 17:07:53 +00:00
jon
5ba685b541 Try harder to remove all copies of references to old files. 2021-02-17 16:57:01 +00:00
jon
7a59cad288 Remove more no-longer-generated files from component.xml 2021-02-17 15:54:27 +00:00
jon
9d2acbd96d Bump to latest version of Bluestuff. 2021-02-17 14:59:31 +00:00
jon
059f189bba Attempt to add all current source files to componenet.xml. 2021-02-17 14:35:49 +00:00
Alexandre Joannou
4c19a34eda Workaround for scheduling issues when using PERFORMANCE_MONITORING (with jdw57) 2021-02-15 18:07:08 +00:00
Marno van der Maas
e3b776a81f Clarified supported versions of verilator 2021-02-12 09:49:17 +00:00
jon
9e36ff95cd Roll back accidental commit of experimental change. 2021-02-11 12:22:00 +00:00
jon
96be5802a0 Bump BlueStuff with workaround. 2021-02-10 17:23:46 +00:00
jon
40ea082310 Some updates to build with the new bsc compiler. 2021-02-10 17:22:26 +00:00