Cheri-research/Toooba
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72 Commits

Author SHA1 Message Date
Jonathan Woodruff
5c6e348788 Missing width extensions. 2023-01-17 16:11:52 +00:00
Jonathan Woodruff
f5450a1c06 Extend ID field to match current design. 
This is likely to be cause of lockup in hardware.
 2023-01-16 17:45:07 +00:00
Alexandre Joannou
95f554dad1 removed coreW from component.xml 2022-08-16 12:44:00 +00:00
Jonathan Woodruff
6ea972931d Add missing verilog file that is inadvertantly used. 2022-02-23 16:46:43 +00:00
Peter Rugg
ac89600601 Add missing TSO dummy store buffer to component.xml 2021-04-23 16:33:26 +01:00
Jonathan Woodruff
db08e96596 Add Btb to the component.xml. 2021-03-03 20:27:31 +00:00
Peter Rugg
53eb073fb2 Don't track generated Verilog 2021-02-19 19:45:00 +00:00
jon
1fbf786294 Add to synthesis file set. 2021-02-17 21:26:54 +00:00
jon
eaf7a4ace7 Add one more missing file and clean up some duplicates. 2021-02-17 18:37:52 +00:00
jon
5ba685b541 Try harder to remove all copies of references to old files. 2021-02-17 16:57:01 +00:00
jon
7a59cad288 Remove more no-longer-generated files from component.xml 2021-02-17 15:54:27 +00:00
jon
059f189bba Attempt to add all current source files to componenet.xml. 2021-02-17 14:35:49 +00:00
Jessica Clarke
fb5339e9ca Adapt the PLIC instantiation and wiring to support multiple cores 2021-01-31 17:54:43 +00:00
Jessica Clarke
6c98dcb3d8 src_SSITH_P3: Delete stray file references 
No clue what mkAxiLowPower is. mkPLIC_16_CoreNumX2_7 belongs with the
dual-core fixes, which aren't in the CHERI branch, at least not
currently (and the old mkPLIC_16_2_7 is still referenced in this file
anyway).
 2021-01-13 00:59:46 +00:00
Jonathan Woodruff
69c697daf7 Changes needed to build for FPGA. 2020-11-06 11:44:33 +00:00
Jessica Clarke
72f49a1109 Regenerate verilog 2020-07-16 19:35:51 +01:00
Jessica Clarke
682ff10d72 Regenerate verilog 2020-07-15 03:16:24 +01:00
Jessica Clarke
e8c1de7793 Regenerate verilog 2020-07-14 19:01:47 +01:00
Jessica Clarke
e89f7a8130 Regenerate verilog 2020-07-13 18:54:53 +01:00
Jessica Clarke
ece8423119 Regenerate verilog 2020-07-11 17:26:00 +01:00
Jessica Clarke
40f8109263 Regenerate verilog 2020-07-06 19:32:56 +01:00
Jessica Clarke
9c12b97a09 Regenerate verilog 2020-07-06 01:55:30 +01:00
Jessica Clarke
cd8e2a15ef Regenerate verilog 2020-07-02 03:00:55 +01:00
Peter Rugg
dcc506a365 Regenerate verilog 2020-07-01 17:08:08 +01:00
Peter Rugg
f8972768a2 Regenerate verilog 2020-06-30 00:00:29 +01:00
Peter Rugg
258a0921e6 Regenerate verilog 2020-06-25 16:23:40 +01:00
Peter Rugg
a5578a715a Regenerate verilog 2020-06-24 21:16:57 +01:00
Peter Rugg
7d866f85e7 Regenerate verilog 2020-06-17 13:02:20 +01:00
Peter Rugg
8778369fe5 Merge remote-tracking branch 'upstream/master' into CHERI 2020-06-17 13:01:41 +01:00
Peter Rugg
3117fcc9d5 Regenerate verilog 2020-06-07 16:52:34 +01:00
Peter Rugg
4fbabae1dd component.xml fixes for synthesis 2020-06-07 16:52:29 +01:00
Peter Rugg
be2c92b291 Regenerate verilog 2020-06-05 17:49:32 +01:00
Peter Rugg
962ade1092 Fixes for synthesis 2020-06-05 17:40:28 +01:00
Peter Rugg
046319b909 Remove Tandem verification 2020-06-03 22:28:31 +01:00
rsnikhil
a6a227ed66 Incorporated patches/additions from Joe Stoy after GFE debugging (w. amendment ...) 
Amendment: RegUNInit.v updated, removing an extraneous RST line.
 2020-03-13 16:38:54 -04:00
rsnikhil
c278e4fe68 Fixed a bug, and a related Tandem-Verification bug, re. CSR MIP MEIP/MTIP/MSIP. 
Two of these were not properly restricted as read-only from CSRRX instructions,
and there was a bug in the WARL function for writing MIP,
and there was a bug in the TV-reporting of MIP updates.
 2020-03-12 21:44:00 -04:00
rsnikhil
f02e9af515 Improved avoidance of initial timer interrupt in MMIOPlatform; removed spurios MSTATUS TV report on CSRRS/C with rs1==0 2020-03-11 22:42:18 -04:00
rsnikhil
a19eb97f34 Small tweak to MMIOPlatform.bsv to avoid spurious timer interrupt at start of time. 2020-03-09 22:58:04 -04:00
rsnikhil
b00f1d2eec Fixed a Tandem Verification trace generation bug for FMV.X.F and FMV.X.D 
We were reporting the incremental value of fflags (=0)
instead of the final value of fflags (same as pre-value, which may not be 0).
 2020-03-09 14:47:20 -04:00
rsnikhil
976494a8ff Fixed Tandem-Verification trace generation issue re. MSTATUS on CSRRx instructions that write to FCSR. 
When a CSRRx instruction writes to FCSR/FFLAGS/FRM, the CPU also
changes MSTATUS.FS and, by implication, MSTATUS.SD because the
floating point state has become "dirty".  Tandem Verification
trace-generation was not reporting this update.
 2020-03-08 21:29:30 -04:00
rsnikhil
fafd99c983 Fixes reported by Joe Stoy: PLIC, MMIO_AXI4_Adapter and Core.bsv (details below) 
PLIC: updated to latest version from Piccolo/Flute.

MMIO_AXI4_Adapter: added workaround for Xilinx IP problem on 64-bit
    AXI4 fabrics. Writes that specify 8-byte size, but only write in
    upper or lower word using strobes, are converted into 4-byte size.

Core.bsv: added a notification to the Debug Module re. CPU halt.
 2020-03-08 15:39:57 -04:00
rsnikhil
4bdbcbfd88 Additional fix to previous commit (75df204e) which only fixed MIP/MIE; this fixes SIP/SIE as well. 2020-03-04 13:14:31 -05:00
rsnikhil
75df204e31 Fixed a Tandem-Verification bug (reporting incorrect MIP/MIE/SIP/SIE post-write values) 
MIP/MIE/SIP/SIE fields are WARL (Write-Any/Read-Legal). The CSR
register forces the user-privilege bits ([8,4,0]) to 0 since riscy-ooo
does not support user-level interrupts.  However, function
Csrfile.fv_warl_xform() was not mirroring this correctly.
 2020-03-04 09:50:39 -05:00
rsnikhil
40b55d2c32 Fixed a Tandem-Verification issue (report MIP change due to interrupts). 
CSR MIP can change due to external/timer interrupts.  These non-instruction-related
changes were not being reported to the Tandem Verifier.
 2020-03-03 18:34:00 -05:00
rsnikhil
ac6043ce2d Fixed two bugs: (1) not trapping on unimplemented CSRs (2) MSTATUS.FS initialization 
(1) riscy-ooo was mapping all unimplemented CSRs to a benign, user-privilege read-write CSR
    Instead, we now catch this RenameStage and steer it to a trap.
(2) MSTATUS.FS was initialized to 2'b00 (absent/off); should be 2'b01 (present and initial)
 2020-03-03 13:56:31 -05:00
rsnikhil
e02dac1449 In CsrFile.bsv, changed user-privilege bits in MIP/SIP/MIE/SIE to read-only 0 since MISA.N=0 2020-03-02 16:20:07 -05:00
rsnikhil
96a0897bf5 In MMIO_AXI4_Adapter.bsv, added check for unmapped addresses, provide err response immediately. 
Previously, the request went out into the fabric, and we were relying
on the fabric returning an error response.  Some fabrics don't do this
reliably, so this removes that reliance on the fabric.
 2020-02-28 14:07:45 -05:00
Niraj N Sharma
6f5d079e7c Modified synth and sim compile options in the Makefile 
Regenerated synth and sim RTLs
 2020-02-22 17:51:13 +05:30
rsnikhil
ddcb784297 Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point. 2020-02-12 10:44:30 -05:00
Niraj Sharma
a99f046cdc Regenerated RTL in src_SSITH_P3 with TANDEM_VERIF 2020-02-12 09:24:33 +05:30