Commit Graph

16 Commits

Author SHA1 Message Date
Jessica Clarke
badf5c8e37 Include xCHERI in ARCH and build directory names
Also use RVFI_DII not RVFIDII in the directory names.

This makes everything match Piccolo/Flute rather than having Toooba be a
weird, inconsistent and plain wrong.
2020-07-05 21:41:28 +01:00
Jessica Clarke
0b0b863baa Replace home-grown dependency script with Bluespec-provided makedepend.tcl
This one has the advantage of being able to be called with the same
flags as bsc, rather than needing to pass things through special
environment variables. As a result, revert all our changes to dealing
with BSC_COMPILATION_FLAGS (some of this diff therefore looks strangely
formatted, but it's to match upstream verbatim, and should be left that
way to minimise diffs and avoid conflicts).
2020-07-05 21:26:18 +01:00
Peter Rugg
8778369fe5 Merge remote-tracking branch 'upstream/master' into CHERI 2020-06-17 13:01:41 +01:00
Peter Rugg
4f4bbbbdcb Add new TagController parameters to synth makefile 2020-06-17 11:40:23 +01:00
Peter Rugg
962ade1092 Fixes for synthesis 2020-06-05 17:40:28 +01:00
Peter Rugg
046319b909 Remove Tandem verification 2020-06-03 22:28:31 +01:00
rsnikhil
a6a227ed66 Incorporated patches/additions from Joe Stoy after GFE debugging (w. amendment ...)
Amendment: RegUNInit.v updated, removing an extraneous RST line.
2020-03-13 16:38:54 -04:00
Niraj N Sharma
6f5d079e7c Modified synth and sim compile options in the Makefile
Regenerated synth and sim RTLs
2020-02-22 17:51:13 +05:30
Niraj Sharma
568f52fc0b Corrected typo in src_SSITH_P3 Makefile 2020-02-14 21:52:20 -05:00
Niraj Sharma
a99f046cdc Regenerated RTL in src_SSITH_P3 with TANDEM_VERIF 2020-02-12 09:24:33 +05:30
Niraj Sharma
e35c48efff Merged src_SSITH_P3 and src_SSITH_P3_sim 2020-02-07 21:00:50 +05:30
rsnikhil
4a7dd01023 Removed -D EXTERNAL_DEBUG_MODULE in src_SSITH_P3 Makefile, and added an undef in src_Core/Core/CoreW.bsv 2020-01-23 12:25:21 -05:00
Niraj Nayan Sharma
364b1d1cf3 For src_SSITH_P3 builds, added conditions to include/exclude
simulation models of the integer divider
2020-01-03 16:59:34 +05:30
Darius Rad
4d1030df47 Add support for external debug module. 2019-04-09 14:08:36 -04:00
rsnikhil
47985fa93f Updated Makefiles so in src_SSITH_P3, RTL refers to Xilinx FP RTL instead of simulation models 2019-04-04 13:10:45 -04:00
rsnikhil
113f888d37 Added support for 'debug_external_interrupt_req'
New method 'debug_external_interrupt_req' to support emulation of a
debug module starts at P3_Core interface and is plumbed all the way in
to the CSR register MIP as interrupt [14].  The corresponding MIE[14]
is always 1, so it is never masked. Still todo: should not be masked
by MSTATUS interrupt-enables either.  Also expanded
interrupt-detection logic, mcause etc. to extend up to interrupt 14.

Builds in standalone mode, runs ISA tests.

Builds in src_SSITH_P3, generating RTL.
2019-04-01 12:26:54 -04:00