Cheri-research/Toooba
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6a317d1a00a167ccfadae0ced9fde5604803f0c0
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187 Commits

Author SHA1 Message Date
Peter Rugg
6a317d1a00 Prevent instruction fetch to unexpected devices 2020-07-10 17:35:06 +01:00
Jessica Clarke
5e9b478371 Cover interesting fetch and rename state for DEBUG_WEDGE configs 2020-07-10 15:59:40 +01:00
Jessica Clarke
0f65994955 Plumb through a lot more ROB debug state 
In particular, the previous set of debug info only looked at one of the
superscalar ways, assuming the 0th was always the next instruction, but
there's a level of indirection to map ports to ways that was missed. But
now we dump out both ways and more. And yes, I fully recognise the
atrocity that is the type in use here... please forgive me. It doesn't
help that bsc is buggy and gets confused about the structure of nested
tuples[1].

Drops the commit debug output to only the low 32 bits of PCC's address
and no instruction bits; as this has been committed it should be (and
has always been observed to be) within bounds and, thus, fit in 32 bits
when running in M-mode, with the instruction bits obtainable from the
binary. I'd much rather know about potentially-dodgy speculative
addresses than things we can reliably infer given the limited number of
DMI registers free (though we could hijack other encodings if
necessary).

[1] https://github.com/B-Lang-org/bsc/issues/199
 2020-07-10 15:59:40 +01:00
jon
a0c5d5a9af Roll back changes to SpecPoisonFifo which were accidentally committed. 2020-07-09 15:19:39 +01:00
jon
59eddfbb4c Move register in reorder buffer that is only used for Tandem 
Verification to that case only.
 2020-07-09 10:26:08 +01:00
jon
40b44d51e2 Merge branch 'CHERI' of https://github.com/CTSRD-CHERI/Toooba into CHERI 2020-07-08 12:45:43 +01:00
jon
0b8a031184 Checkpoint FIFO scheduler work. 2020-07-08 12:39:13 +01:00
Jessica Clarke
68d3bd484e Provide opt-in wedge debugging info 
When DEBUG_WEDGE is defined, expose the last committed and next in the
reorder buffer PC and corresponding instruction via DMI registers, since
even when the core is wedged and we can't read GPRs etc we can still
interact with the debug module itself. Hopefully this proves useful for
debugging wedges.
 2020-07-07 23:59:35 +01:00
Peter Rugg
c406d357c9 Add CHERI+RVFI_DII grant codes and copyrights 2020-07-06 17:39:25 +01:00
Peter Rugg
c8e4a64128 Add sentries 2020-06-29 23:29:08 +01:00
jon
a51ddf17be Use the request ID in the response to the DMA interface. 2020-06-20 12:15:49 +01:00
Peter Rugg
8778369fe5 Merge remote-tracking branch 'upstream/master' into CHERI 2020-06-17 13:01:41 +01:00
jon
1de6fc941e Adjust debug output to always print certain portions as this is more 
useful.
 2020-06-11 09:47:19 +01:00
jon
4b3f97cb6a More correct version of select function. 
Also the beginnings of a select function for writes which is not yet
used.
 2020-06-09 12:33:43 +01:00
jon
122e98b0c7 Attempt to provide correct alignment for MMIO requests in flits returned 
to bus.
This does not yet attempt to fix writes which might likely also need
fixing.
 2020-06-08 19:03:12 +01:00
jon
9ec9b34376 Don't overwrite earlier exception in Execute. 2020-06-06 09:42:11 +01:00
Peter Rugg
962ade1092 Fixes for synthesis 2020-06-05 17:40:28 +01:00
Peter Rugg
9aeb8f1ea9 Fix CSR read immediate case 2020-06-02 20:50:56 +01:00
jon
bb3eddccf2 Implement cap_mode switch for legacy loads and stores, as the mechanism 
for decoding has changed and was not setting the new flag.
 2020-06-02 19:00:28 +01:00
Peter Rugg
675de23dc2 Fix TestSubset top check the wrong way around 2020-06-01 20:23:42 +01:00
Peter Rugg
b7c73d4422 Link offset in JAL 2020-06-01 18:57:51 +01:00
Peter Rugg
1725cdda8f Fix bug where immediate discarded too early in Scr case 2020-06-01 15:12:30 +01:00
Peter Rugg
f7deb7349b Fix writeback when reading and writing CSR/SCR together 2020-06-01 15:04:59 +01:00
Peter Rugg
16eac986ef Fix EPC/MTVEC updates ignoring old value 2020-06-01 12:17:14 +01:00
Peter Rugg
6a8f0e5bc0 Rename 'cap-mode' in Mem pipeline to ddc offset, since explicit memory instructions contradicting the cap_mode exist 2020-05-29 17:05:03 +01:00
Peter Rugg
a7d4d8e4a4 Fix bug where explicit cap-rel mem accesses would always trap as untagged 2020-05-29 16:43:20 +01:00
Peter Rugg
a49d3d2b6b Add ASR restrictions 2020-05-28 23:25:33 +01:00
jon
8ae5d3a1b2 Build RVFI_DII Toooba with very small caches, 2-way set associative to 
maximise cache and memory verification.
 2020-05-28 10:59:08 +01:00
Peter Rugg
57129f6383 Some minor cleanup of decode 2020-05-21 15:51:03 +01:00
Peter Rugg
2702f40b5e Initial implementation of CSetBoundsExact 2020-05-21 15:50:37 +01:00
Peter Rugg
791e862377 Initial (slow) implementation of CTestSubset 2020-05-21 15:49:25 +01:00
jon
0a84227f93 Implement DDC offset. 2020-05-20 18:03:14 +01:00
jon
d00ade6c9d Fix new-write-folding-in function to copy original tags where there are 
no byte-enables set.
 2020-05-20 13:31:09 +01:00
Peter Rugg
072c188f92 Initial implementation of CCSeal 2020-05-19 23:05:18 +01:00
Peter Rugg
61b97e090d Fix CFromPtr common case 2020-05-19 23:04:53 +01:00
Peter Rugg
e74220afc4 Implement CFromPtr 2020-05-19 02:37:53 +01:00
Peter Rugg
cd4d296a0c Initial attempt to allow reads/writes to xtvec, xepc via xtcc, xepcc 2020-05-14 17:22:39 +01:00
jon
82498cd963 Only unseal next_pc after exception checks have been made. 2020-05-13 12:48:23 +01:00
Peter Rugg
7c0dad18d6 Deal with separate kinds of sealing more explicitly 2020-05-13 12:02:03 +01:00
jon
a6fd7acf3e Temporary resolution of signExtension behaviour for getType. 
Peter intends to use getKind from an updated version of cheri-cap-lib.
 2020-05-12 17:25:44 +01:00
jon
0f0d1a983b Remove references to ScrFile which were mysteriously still here. 2020-05-12 17:24:50 +01:00
Peter Rugg
c65e89f6c1 Also enforce privilege checks for SCR reads 2020-05-12 13:28:40 +01:00
jon
854151978e Fix byte-enable merging tag logic in the cache (with help from 
Alexandre).
Also adjust priority in CCall exceptions.
 2020-05-12 12:25:45 +01:00
Peter Rugg
26919154db Merge branch 'pdr32-wip' into CHERI 2020-05-12 00:19:36 +01:00
Peter Rugg
8f4c6fbcce Decode CSpecialRW 0 as AUIPCC 2020-05-11 23:52:43 +01:00
Peter Rugg
f0bcd2ccd1 Don't write on CSpecialRW from R0 2020-05-11 23:52:04 +01:00
Peter Rugg
ec9f19dc26 Disable assert since normal instructions can read SCRs 2020-05-11 22:39:12 +01:00
Peter Rugg
20eb1129b1 Complete PCC checks 2020-05-11 17:25:21 +01:00
Peter Rugg
0ee9c65f3a Forward cap-only instructions to the ALU 2020-05-11 17:24:43 +01:00
Peter Rugg
461ca6a703 Merge branch 'CHERI' into pdr32-wip 2020-05-11 14:08:42 +01:00