8 Commits

Author	SHA1	Message	Date
rsnikhil	83829590dd	Fixed up logic for "Non-Debug-Module reset" request/response from the Debug Module ... Now able to run multiple ISA tests in a single simulation run connected to remote debugger DSharp, using either hart_reset or ndm_reset between tests to bring the system back into reset state. All Debug Module commands working: - dm_reset, hart_reset, ndm_reset - break (set breakpoint) - step - continue (until breakpoint of 'halt' command) - halt - read/write GPR, FPR, CSR, memory - elf_load	2020-02-04 16:02:53 -05:00
rsnikhil	0f04b9cbe1	Tweaks to builds/Resources/Include_..._.mk	2020-01-08 19:49:49 -05:00
James Clarke	7ecde58b1d	Add RV64ACDFIMSU_Toooba_bluesim build	2020-01-04 22:44:59 +00:00
Niraj Nayan Sharma	601bbe5a82	No longer using Xilinx FPU modules	2019-12-14 12:44:02 +05:30
rsnikhil	666dd2ad92	Small tweak to remove unnecessary explicit boot rom addrs (subsumed by IO)	2019-04-22 15:12:30 -04:00
rsnikhil	51bdff05d8	Updated Run_regression.py to utilize parallel processes	2019-04-18 18:42:06 -04:00
rsnikhil	47985fa93f	Updated Makefiles so in src_SSITH_P3, RTL refers to Xilinx FP RTL instead of simulation models	2019-04-04 13:10:45 -04:00
rsnikhil	ee24a93944	Initial load of files	2019-03-26 14:49:40 -04:00