Cheri-research/Toooba
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e3664c2bfd5752cce1143aa421bdfcfc8a974dc9
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126 Commits

Author SHA1 Message Date
jon
e3664c2bfd Do sign extension properly on loads. 2020-05-07 12:17:14 +01:00
jon
9c0130a200 Support for permissions and bounds checks for memory operations, taking 
the cap mode into account.
 2020-05-06 18:48:44 +01:00
jon
cbb0d859c7 Feed capability checks and bounds checks into the memory pipe and back 
into the reorder buffer.
 2020-05-05 18:28:28 +01:00
jon
500811430b Initial support for decoding Capability Memory instructions. 2020-05-05 12:23:10 +01:00
jon
21d1207e6b The beginnings of an implementation of LQ and SQ. 
Also a bug-fix to unseal nextPCC for control flow instructions, which
should only affect CCall (which was leaving PCC sealed).
 2020-05-01 17:26:41 +01:00
jon
0177c2cd6e Use the bounds of PCC to check legacy control flow instructions rather 
than the bounds of the newPCC after C(Set/Inc)Offset, which may have
become unrepresentable.
 2020-05-01 12:17:20 +01:00
jon
90d9d7cbc7 Move back to considering the instruction width when checking PCC. 2020-04-30 15:33:01 +01:00
Alexandre Joannou
b70498e00a Try new types to hold capabilities 2020-04-30 14:07:37 +01:00
jon
0b68498940 Fix interface with special capability register file trap handling. 
Call the correct trap function, and report the correct privilege level.
 2020-04-30 12:00:55 +01:00
jon
44199a841b Only check the bounds of nextPc if the branch is taken... 2020-04-29 18:34:02 +01:00
jon
1439fe98c7 Fix 2 bugs. 
Restore from sepc on sret.
To "inclusive" bounds check on Jumps and Branches.
 2020-04-29 13:42:23 +01:00
jon
d3e0908785 Check PCC bounds in rename. 2020-04-28 19:08:07 +01:00
jon
ab6b8966db Bounds-check legacy jalr and br correctly. 2020-04-28 11:47:09 +01:00
jon
f63d55d4e5 Fix bug; consistently treat mepc as the offset of mepcc. 
Also remove PCC from the SCR file.
 2020-04-27 17:36:02 +01:00
Alexandre Joannou
e5b7ba6b13 Fixes to build with cap PCC for non RVFI-DII case 2020-04-27 16:48:34 +01:00
jon
5693af05e5 Changes to make PCC consistent. 
Specifically, attach the bounds to PC all the way back into the branch predictors.
 2020-04-27 15:13:36 +01:00
jon
2251457840 Implement target bounds-check for CJALR. 2020-04-23 17:54:18 +01:00
Peter Rugg
3b30d2db36 Add BuildCap unsealing 2020-04-22 15:52:23 +01:00
Peter Rugg
8cc8f71cb9 Perform bounds check on requested length rather than rounded length. 
This prevents issues with overflow in the top, and should be correct
based on the rounding used in the SetBounds function.
 2020-04-22 14:27:11 +01:00
Peter Rugg
a89a606a6d Factor out Opcodes and CSRs into separate files 2020-04-21 20:36:56 +01:00
Peter Rugg
3693326b62 Don't sign extend CSetBoundsImm immediate 2020-04-21 16:45:04 +01:00
Peter Rugg
8a4fa786dd Add CToPtr special case 2020-04-21 13:52:33 +01:00
Peter Rugg
1773530c72 Attempt to enable AUIPCC 2020-04-20 23:11:58 +01:00
Peter Rugg
923d4915cb Make SetBounds legal 2020-04-20 23:05:26 +01:00
Peter Rugg
8e01cf68df More concise FShow for CapChecks 2020-04-20 21:28:09 +01:00
Peter Rugg
b4be80eba1 Bounds Check fixes 2020-04-20 21:23:42 +01:00
Peter Rugg
7db3fa539f Add ALU bounds check 2020-04-20 11:21:51 +01:00
Peter Rugg
1bb53e5e86 Merge branch 'CHERI' into pdr32-wip 2020-04-16 20:58:37 +01:00
Peter Rugg
f1e04486b7 Work on SCR-related instructions 2020-04-16 20:53:08 +01:00
Peter Rugg
8269a0625e Initial implementation of set bounds 2020-04-16 20:39:54 +01:00
jon
4b2c3b1114 An attempt at doing the "right thing" with Jr targets and links with respect to PCC. 
This is not easy to test until we have CSetBounds.
 2020-04-16 18:07:39 +01:00
jon
a77ecc59af Checkpoint work to propagate register numbers into the exception code. 
There's another half of this left to do to propagate all the way into the CSR file.
 2020-04-16 17:28:28 +01:00
jon
9bb3e835ac Fix operand of CCall. 
Also fix one case of CCopyType where it is meant to return nullWithAddr(-1).
 2020-04-16 11:38:38 +01:00
jon
c056d40a3a Trace the register that has been decoded rather than picking out the bits from the instruction. 
Duh.
 2020-04-15 14:08:36 +01:00
Peter Rugg
a0fb527ad7 Raise illegalInstruction for currently unsupported exceptions 2020-04-15 14:07:36 +01:00
Peter Rugg
e773cb0232 Add CIncOffsetImm 2020-04-15 14:06:46 +01:00
jon
9685bf1931 Implement CCall, hopefully as well as CJALR. 
This passes the unmodified TestRIG routine for CHERI Control Flow, which is very promising indeed!
There are some cases that are not covered there, but a lot is covered.
 2020-04-14 18:10:53 +01:00
Peter Rugg
72dc8f8bad Fix cap instructions not being sent to ALU 2020-04-07 19:55:09 +01:00
jon
56885f06c0 Changes for CJALR-only TestRIG to work. 
This includes replacing register read values with nullCap if reading x0, which is generally necessary.
This is more-or-less using a new mechanism which shouldn't actually be necessary if the default value in the register file is nullCap.
(In RVFI_DII, we initialise with the almightyCap instead.)
 2020-04-07 16:32:31 +01:00
jon
2918854bbc Add missing ifdef. 2020-04-07 12:37:14 +01:00
jon
850e632140 Changes for CJALR to work in a basic case, as well as piping CHERI exceptions through to commit, though the register isn't piped and I've undone some useful work for that piping. Oh well. 2020-04-06 18:18:05 +01:00
Peter Rugg
4ce8f54903 Add initial exception checks 2020-04-06 12:26:19 +01:00
jon
1ecdf73dd3 Make CJALR work like JALR but without an immediate. Seems to work! 
Obviously doesn't throw capability exceptions yet...
 2020-04-03 17:57:57 +01:00
jon
d07d6f4761 Add OpCHERI to the function that rationalises opcodes. 2020-04-03 16:42:14 +01:00
Peter Rugg
f20c644bae Add startings of decoding 2020-04-02 21:08:59 +01:00
jon
2c6ad40f93 Check the already decoded destination to decide to populate the register write data field in RVFI. 2020-04-02 17:10:52 +01:00
jon
b656f46859 Both enable tracing of floating-point register writes in RVFI-DII, and then properly not use them (since we're not expected to). 
This is better than using nonsense as we were previously doing on floating point instructions.
 2020-04-02 16:28:18 +01:00
jon
7618c5cec8 Trap on access of fcsr when floating point is not enabled. 2020-04-02 13:05:42 +01:00
jon
4714070aef Trace the next PC correctly for mret. 2020-04-01 18:43:48 +01:00
Jonathan Woodruff
81da99237e Move the register file to CapReg format, and pipe CapPipe around the pipeline. 2020-03-31 15:44:23 +01:00